XR16M2752IJ44 EXAR [Exar Corporation], XR16M2752IJ44 Datasheet - Page 51

• Manufacturer Part Number: XR16M2752IJ44
• Description: HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
• Manufacturer: EXAR [Exar Corporation]

REV. P1.0.0
GENERAL DESCRIPTION................................................................................................ 1
PIN DESCRIPTIONS ........................................................................................................ 3
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 6
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 7
3.0 UART INTERNAL REGISTERS............................................................................................................. 21
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 23
A
F
ORDERING INFORMATION
EATURES
PPLICATIONS
2.1 CPU INTERFACE ................................................................................................................................................ 7
2.2 DEVICE RESET ................................................................................................................................................... 7
2.3 DEVICE IDENTIFICATION AND REVISION ....................................................................................................... 7
2.4 CHANNEL A AND B SELECTION ...................................................................................................................... 7
2.5 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................... 8
2.6 DMA MODE ......................................................................................................................................................... 8
2.7 INTA AND INTB OUTPUTS................................................................................................................................. 9
2.8 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT................................................................................ 9
2.9 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 10
2.10 TRANSMITTER................................................................................................................................................ 12
2.11 RECEIVER ....................................................................................................................................................... 13
2.12 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 15
2.13 AUTO RTS HYSTERESIS .............................................................................................................................. 15
2.14 AUTO RS485 HALF-DUPLEX CONTROL ..................................................................................................... 15
2.15 AUTO CTS FLOW CONTROL........................................................................................................................ 15
2.16 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 17
2.17 SPECIAL CHARACTER DETECT.................................................................................................................. 17
2.18 INFRARED MODE ........................................................................................................................................... 18
2.19 SLEEP MODE WITH AUTO WAKE-UP ......................................................................................................... 19
2.20 INTERNAL LOOPBACK................................................................................................................................. 20
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 23
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 23
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 23
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 25
F
F
F
T
T
T
T
F
F
T
F
F
F
F
F
T
F
F
T
T
IGURE
IGURE
IGURE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
ABLE
ABLE
2.10.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY......................................................................................... 12
2.10.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 12
2.10.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 12
2.11.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY ............................................................................................ 13
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 24
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 24
1: C
2: TXRDY#
3: INTA
4: INTA
5: T
6: A
7: UART CHANNEL A AND B UART INTERNAL REGISTERS ...................................................................................... 21
8: INTERNAL REGISTERS DESCRIPTION. S
1. XR16M2752 B
2. P
3. XR16L2750 D
4. T
5. B
6. T
7. T
8. R
9. R
10. A
11. I
12. I
.................................................................................................................................................... 1
YPICAL DATA RATES WITH A
HANNEL
UTO
YPICAL OSCILLATOR CONNECTIONS
RANSMITTER
RANSMITTER
IN
AUD
ECEIVER
ECEIVER
NFRARED
NTERNAL
UTO
.............................................................................................................................................. 1
O
AND
AND
X
UT
R
ON
RTS
ATE
A
AND
A
INTB P
INTB P
/X
SSIGNMENT
O
O
AND
L
OFF
T
G
PERATION IN NON
PERATION IN
OOP
AND
RANSMIT
RXRDY# O
ENERATOR
O
O
ATA
LOCK
............................................................................................................................... 2
B S
PERATION IN NON
PERATION IN
(S
INS
IN
CTS F
B
OFTWARE
B
ACK IN
ELECT
O
US
O
D
PERATION
..................................................................................................................................................... 2
D
IAGRAM
PERATION FOR
I
ATA
LOW
NTERCONNECTIONS
............................................................................................................................................... 11
FIFO
UTPUTS IN
C
............................................................................................................................................... 8
24 MH
) F
HANNEL
E
FIFO
C
-FIFO M
NCODING AND
........................................................................................................................................ 1
LOW
ONTROL
AND
TABLE OF CONTENTS
F
OR
-FIFO M
Z CRYSTAL OR EXTERNAL CLOCK AT
AND
................................................................................................................................. 9
C
A
FIFO
A
R
UTO
ONTROL
T
ODE
ECEIVER
AND
RANSMITTER
O
F
LOW
PERATION
ODE
AND
RTS F
.................................................................................................................... 14
B ................................................................................................................ 20
.................................................................................................................... 7
R
HADED BITS ARE ENABLED WHEN
ECEIVE
C
.............................................................................................................. 12
............................................................................................................... 17
DMA M
ONTROL
............................................................................................................... 9
LOW
....................................................................................................... 16
........................................................................................................ 9
I
D
C
ODE
ATA
ONTROL
M
ODE
D
............................................................................................. 8
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
ECODING
..................................................................................... 13
M
ODE
16X S
.......................................................................... 18
......................................................................... 14
AMPLING
EFR B
IT
................................................... 11
-4=1 ......................................... 22
XR16M2752