XR16M2752IJ44 EXAR [Exar Corporation], XR16M2752IJ44 Datasheet - Page 38
XR16M2752IJ44
Manufacturer Part Number
XR16M2752IJ44
Description
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
Manufacturer
EXAR [Exar Corporation]
Datasheet
1.XR16M2752IJ44.pdf
(52 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16M2752IJ44-F
Manufacturer:
Exar Corporation
Quantity:
10 000
XR16M2752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts HIGH at the next upper trigger level or hysteresis level. RTS# will return LOW when FIFO data
falls below the next lower trigger level. The RTS# output must be asserted (LOW) before the auto RTS can
take effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.
•
•
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
•
•
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see
4.19.1
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.
Data transmission resumes when CTS# returns LOW.
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
Table
6.
38
REV. P1.0.0