AK4343EN AKM [Asahi Kasei Microsystems], AK4343EN Datasheet - Page 92

• Manufacturer Part Number: AK4343EN
• Description: Stereo DAC with HP/RCV/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
MS0478-E-01
(Addr:05H, D5&D2-0)
(Addr:09H&0CH, D7-0)
(Addr:0AH&0DH, D7-0)
Stereo Line Output
(Addr:02H, D4)
(Addr:03H, D6)
(Addr:00H, D2)
(Addr:00H, D5)
(Addr:00H, D3)
<Example>
DVL/R7-0 bits
PMDAC bit
PMMIN bit
IVL/R7-0 bits
ROUT pin
DACL bit
LOUT pin
LOPS bit
PMLO bit
FS3-0 bits
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). When the AK4343 is PLL mode, DAC and Stereo Line-Amp
(2) Set up the path of “DAC
(3) Set up the ALC Block Digital Volume (Addr: 09H and 0CH)
(4) Set up the output digital volume (Addr: 0AH and 0DH)
(5) Enter power-save mode of Stereo Line Amp: LOPS bit = “0”
(6) Power-up DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMMIN = PMLO bits = “0” → “1”
(7) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1”
(8) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0”
(9) Power-down DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMMIN = PMLO bits = “1” → “0”
(10) Disable the path of “DAC
(11) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1”
AVL7-0 and AVR7-0 bits should be set to “91H”(0dB).
should be powered-up in consideration of PLL lock time after the sampling frequency is changed.
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1”. The
initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital
data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input
data after the initialization cycle is complete. When ALC bit is “1”, ALC is disable (ALC gain is set by
AVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle,
ALC operation starts from the gain set by AVL/R7-0 bits.
LOUT and ROUT pins rise up to VCOM voltage after PMLO bit is changed to “1”. Rise time is 300ms(max)
at C=1µF and AVDD=3.3V.
LOPS bit should be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation
by setting LOPS bit to “0”.
LOUT and ROUT pins fall down to AVSS. Fall time is 300ms(max) at C=1µF and AVDD=3.3V.
LOPS bit should be set to “0” after LOUT and ROUT pins fall down.
0,000
E1H
18H
(1)
(2)
(4)
(3)
(5)
Stereo Line Amp”: DACL bit = “0”
(6)
>300 ms
Stereo Line-Amp”: DACL bit = “1”
Figure 82. Stereo Lineout Sequence
(7)
1,111
Normal Output
91H
28H
- 92 -
(8)
(9)
(10)
>300 ms
“1”
“0”
“0”
“1”
(11)
“1”
“0”
Example:
PLL, Master Mode
Digital Volume: −8dB
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
(6) Addr:00H, Data:6CH
LOVL=MINL bits = “0”
(1) Addr:05H, Data:27H
(2) Addr:02H, Data:10H
(5) Addr:03H, Data:40H
(7) Addr:03H, Data:00H
(8) Addr:03H, Data:40H
(9) Addr:00H, Data:40H
(3) Addr:09H&0CH, Data:91H
(4) Addr:0AH&0DH, Data:28H
(10) Addr:02H, Data:00H
(11) Addr:03H, Data:00H
Playback
[AK4343]
2006/10