AK4343EN AKM [Asahi Kasei Microsystems], AK4343EN Datasheet - Page 26

• Manufacturer Part Number: AK4343EN
• Description: Stereo DAC with HP/RCV/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
1) PLL Master Mode (AIN3 bit = “0”; PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0”
Table 8).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
2) PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0”
After that, the clock selected by Table 10 is output from MCKO pin when PLL is locked. DAC output invalid data when
the PLL is unlocked. The output signal should be muted by writing “0” to DACL, DACH and DACS bits.
MS0478-E-01
PLL State
After that PMPLL bit “0”
PLL Unlock (except above case)
PLL Lock
PLL Unlock State
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
After that PMPLL bit “0”
PLL Unlock
PLL Lock
“1”
MCKO bit = “0”
“L” Output
“L” Output
“L” Output
“1”
MCKO pin
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MCKO bit = “0”
MCKO bit = “1”
“L” Output
“L” Output
“L” Output
See Table 10
“1”. If MCKO bit is “0”, MCKO pin goes to “L” (see
Invalid
Invalid
MCKO pin
MCKO bit = “1”
See Table 11
“L” Output
Invalid
Invalid
Output
BICK pin
Invalid
“L” Output
LRCK pin
1fs Output
Invalid
[AK4343]
2006/10
“1”.