M38062M3-156FP MITSUBISHI [Mitsubishi Electric Semiconductor], M38062M3-156FP Datasheet - Page 15

• Manufacturer Part Number: M38062M3-156FP
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

INTERRUPTS
Interrupts occur by sixteen sources: seven external, eight internal,
and one software.
Interrupt control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
Table 1. Interrupt vector addresses and priority
Note 1: Vector addresses contain interrupt jump destination addresses.
Reset (Note 2)
INT
INT
Serial I/O1
reception
Serial I/O1
transmission
Timer X
Timer Y
Timer 1
Timer 2
CNTR
CNTR
Serial I/O2
INT
INT
INT
A-D converter
BRK instruction
Interrupt Source
0
1
2
3
4
2: Reset function in the same way as an interrupt with the highest priority.
0
1
Priority
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
Vector Addresses (Note 1)
FFDD
FFFD
FFFB
FFEF
FFED
FFEB
FFDF
FFF9
FFF7
FFF5
FFF3
FFF1
FFE9
FFE7
FFE5
FFE3
FFE1
High
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
FFDC
FFFC
FFEE
FFEC
FFEA
FFDE
FFFA
FFF8
FFF6
FFF4
FFF2
FFF0
FFE8
FFE6
FFE4
FFE2
FFE0
Low
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
At reset
At detection of either rising or
falling edge of INT
At detection of either rising or
falling edge of INT
At completion of serial I/O1
data reception
At completion of serial I/O1
transfer shift or when
transmission buffer is empty
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR
At detection of either rising or
falling edge of CNTR
At completion of serial I/O2
data transfer
At detection of either rising or
falling edge of INT
At detection of either rising or
falling edge of INT
At detection of either rising or
falling edge of INT
At completion of A-D conversion
At BRK instruction execution
Interrupt operation
When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering.The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.
Notes on use
When the active edge of an external interrupt (INT
CNTR
quest bit may also be set. Therefore, please take following se-
quence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge selection.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.
Generating Conditions
Interrupt Request
0
, or CNTR
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
0
1
2
3
4
input
input
input
input
input
0
1
input
input
1
) is changed, the corresponding interrupt re-
MITSUBISHI MICROCOMPUTERS
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Non-maskable software interrupt
3806 Group
Remarks
0
to INT
15
4
,