LF3310QC15 LODEV [LOGIC Devices Incorporated], LF3310QC15 Datasheet - Page 9

• Manufacturer Part Number: LF3310QC15
• Description: Horizontal / Vertical Digital Image Filter
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
(see Figure 11). Each round register is
32-bits wide and user-programmable.
This allows the filter’s output to be
rounded to any precision required.
Since any 32-bit value may be
programmed into the round registers,
the device can support complex
rounding algorithms as well as
standard Half-LSB rounding. HRSL
0
horizontal round registers are used in
the rounding operation. A value of 0
T
T
determines which of the sixteen
ABLE
ABLE
BITS
BITS
11-3
11-7
4-1
0
1
2
0
5
6
2. C
3. C
FUNCTION
Reserved
FUNCTION
I/D Register Length
Reserved
ALU Mode
Pass A
Pass B
Odd-Tap Interleave Mode
Horizontal Tap Number
Horizontal Data Reversal
ONFIGURATION
ONFIGURATION
R
R
EGISTER
EGISTER
3-
DESCRIPTION
0 : A + B
1 : B – A
0 : ALU Input A = 0
1 : ALU Input A = Forward Register Path
0 : ALU Input B = 0
1 : ALU Input B = Reverse Register Path
Must be set to “0”
DESCRIPTION
0 : Odd-Tap Interleave Mode Disabled
1 : Odd-Tap Interleave Mode Enabled
0000: 1 Register
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001: 10 Registers
1010: 11 Registers
1011: 12 Registers
1100: 13 Registers
1101: 14 Registers
1110: 15 Registers
1111: 16 Registers
0 : Even Number of Taps
1 : Odd Number of Taps
0 : Data Reversal Enabled
1 : Data Reversal Disabled
Must be set to “0”
on HRSL
register 0. A value of 1 selects hori-
zontal round register 1 and so on.
HRSL
cycle if desired. This allows the
rounding algorithm to be changed
every clock cycle. This is useful when
filtering interleaved data. If rounding
is not desired, a round register should
be loaded with 0 and selected as the
register used for rounding. Round
register loading is discussed in the LF
Interface
0 – A
1 – A
2 Registers
3 Registers
4 Registers
5 Registers
6 Registers
7 Registers
8 Registers
9 Registers
3-0
DDRESS
DDRESS
3-0
TM
may be changed every clock
section.
selects horizontal round
200H
201H
9
Horizontal / Vertical Digital Image Filter
Horizontal Select
The word width of the horizontal
filter output is 32-bits. However, only
12-bits may be sent to the filter
output. The horizontal filter select
circuitry determines which 12-bits are
passed (see Table 1). The horizontal
select registers control the horizontal
select circuitry. There are sixteen
horizontal select registers. Each select
register is 5-bits wide and user-
programmable. HRSL
which of the sixteen horizontal select
registers are used in the horizontal
select circuitry. A value of 0 on
HRSL
register 0. A value of 1 selects hori-
zontal select register 1 and so on.
HRSL
cycle if desired. This allows the 12-bit
window to be changed every clock
cycle. This is useful when filtering
interleaved data. Select register
loading is discussed in the LF
Interface
Horizontal Limiting
An output limiting function is
provided for the output of the
horizontal filter. The horizontal limit
registers determine the valid range of
output values when limiting is
enabled (Bit 1 in Configuration
Register 5). There are sixteen 24-bit
horizontal limit registers. HRSL
determines which horizontal limit
register is used during the limit
operation. A value of 0 on HRSL
selects horizontal limit register 0. A
value of 1 selects horizontal limit
register 1 and so on. Each limit
register contains both an upper and
lower limit value. If the value fed to
the limiting circuitry is less than the
lower limit, the lower limit value is
passed as the filter output. If the
value fed to the limiting circuitry is
greater than the upper limit, the
upper limit value is passed as the
filter output. HRSL
changed every clock cycle if desired.
This allows the limit range to be
Video Imaging Products
3-0
3-0
TM
selects horizontal select
may be changed every clock
section.
3-0
3-0
may be
11/08/2001-LDS.3310-H
determines
LF3310
3-0
3-0