LF3310QC15 LODEV [LOGIC Devices Incorporated], LF3310QC15 Datasheet - Page 10

• Manufacturer Part Number: LF3310QC15
• Description: Horizontal / Vertical Digital Image Filter
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
changed every clock cycle. This is
useful when filtering interleaved
data. When loading limit values into
the device, the upper limit must be
greater than the lower limit. Limit
register loading is discussed in the LF
Interface
Vertical Filter
The vertical filter is designed to filter
a digital image in the vertical dimen-
sion. It is a FIR filter which can be
configured to have as many as 8-taps.
Line Buffers
There are seven on-chip line buffers.
The maximum delay length of each
line buffer is 3076 cycles and the
minimum is 4 cycles. Configuration
Register 2 (CR
length of the line buffers. The line
buffer length is equal to the value of
CR
the line buffer length to 4. A value of
3072 for CR
length to 3076. Any values for CR
greater than 3072 are not valid.
The line buffers have two modes of
operation: delay mode and recirculate
mode. Bit 0 of Configuration Register
3 determines which mode the line
buffers are in. In delay mode, the
data input to the line buffer is delayed
by an amount determined by CR
recirculate mode, the output of the
line buffer is routed back to the input
of the line buffer allowing the line
buffer contents to be read multiple
times.
Bit 1 of Configuration Register 3
allows the line buffers to be loaded in
parallel. When Bit 1 is “1”, the input
register (DIN
buffers in parallel. This allows all the
line buffers to be preloaded with data
in the amount of time it normally
takes to load a single line buffer.
VSHEN enables or disables the
loading of data into the line buffers
when the device is in Dimensionally
Separate Mode (see the VSHEN
2
plus 4. A value of 0 for CR
TM
section.
2
sets the line buffer
11-0
2
) determines the delay
) loads all seven line
2
2
sets
. In
2
section for a full discussion). When in
Orthogonal Mode, VSHEN also
enables or disables the loading of data
into the input register (DIN
the forward and reverse I/D Registers.
It is important to note that in Or-
thogonal Mode, either HSHEN or
VSHEN can disable the loading of
data into the input register (DIN
I/D Registers, and line buffers. Both
must be active to enable data loading
in Orthogonal Mode.
T
T
T
T
ABLE
ABLE
ABLE
ABLE
BITS
BITS
BITS
BITS
11-0
11-2
11-5
11-2
3-2
0
1
0
1
4
0
1
4. C
5. C
6. C
7. C
FUNCTION
Line Buffer Length
FUNCTION
Line Buffer Mode
Line Buffer Load
Reserved
FUNCTION
HV Filter Mode
HV Direction
Orthogonal Kernel Size
Limit Register Load Control 0 : Limit Registers Always Enabled
Reserved
FUNCTION
Vertical Limit Enable
Horizontal Limit Enable
Reserved
ONFIGURATION
ONFIGURATION
ONFIGURATION
ONFIGURATION
10
Horizontal / Vertical Digital Image Filter
11-0
) and
R
R
R
R
11-0
EGISTER
EGISTER
EGISTER
EGISTER
),
DESCRIPTION
See Line Buffer Description Section
DESCRIPTION
0 : Delay Mode
1 : Recirculate Mode
0 : Normal Load
1 : Parallel Load
Must be set to “0”
DESCRIPTION
0 : Orthogonal Mode
1 : Dimensionally Separate
0 : Horizontal to Vertical
1 : Vertical to Horizontal
00 : 3-3 Kernel
01 : 5-5 Kernel
10 : 7-7 Kernel
11 : Not Used
1 : Limit Registers Under Shift Enable Control
Must be set to “0”
DESCRIPTION
0 : Vertical Limiting Disabled
1 : Vertical Limiting Enabled
0 : Horizontal Limiting Disabled
1 : Horizontal Limiting Enabled
Must be set to “0”
Interleaved Data
The vertical filter is capable of
handling interleaved data. The
number of data sets it can handle is
determined by the number of data
values contained in a video line. If
the interleaved video line has 3076
data values or less, the vertical filter
can handle it no matter how many
data sets are interleaved together.
2 – A
3 – A
4 – A
5 – A
Video Imaging Products
DDRESS
DDRESS
DDRESS
DDRESS
202H
203H
204H
205H
11/08/2001-LDS.3310-H
LF3310