SAH-C515 SIEMENS [Siemens Semiconductor Group], SAH-C515 Datasheet - Page 36
![no-image](/images/no-image-200.jpg)
SAH-C515
Manufacturer Part Number
SAH-C515
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.SAH-C515.pdf
(160 pages)
- Current page: 36 of 160
- Download datasheet (912Kb)
condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of
the last 16 verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail
and high for pass) during the 16 bytes are checked. In ROM verification mode 2, the C515 must be
provided with a system clock at the XTAL pins.
Figure 4-5 shows an application example of an external circuitry which allows to verify a protected
ROM inside the C515-1R in ROM verification mode 2. With RESET going inactive, the C515-1R
starts the ROM verify sequence. Its ALE is clocking a 13-bit address counter. This counter
generates the addresses for an external EPROM which is programmed with the contents of the
internal (protected) ROM. The verify detect logic typically displays the pass/fail information of the
verify operation. P3.5 can be latched with the falling edge of ALE.
When the last byte of the internal ROM has been handled, the C515-1R starts generating a PSEN
signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end
of the internal ROM verification.
Figure 4-5
ROM Verification Mode 2 - External Circuitry Example
Semiconductor Group
C515-1R
RESET
Port
PSEN
P3.5
ALE
EA
0
2 k
W
V
CC
CLK
Address
&
&
Counter
13-
Carry
S
Bit
4-8
V
CC
Detect
Verify
Logic
External Bus Interface
A0
D0
CS
- A12
-
Compare
D7
Code
ROM
MCS03223
OE
C515
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