SAH-C515 SIEMENS [Siemens Semiconductor Group], SAH-C515 Datasheet - Page 111

• Manufacturer Part Number: SAH-C515
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

An A/D conversion is always started with the beginning of a processor cycle when it has been
initiated by writing SFR ADDAT. The ADDAT write operation may take one or two machine cycles.
In figure 6-33, the instruction MOV ADDAT,#0 starts the A/D conversion (machine cycle X-1 and
X). The total A/D conversion (sample and conversion phase) is finished with the beginning of the
14th machine cycle after the A/D conversion start. In the next machine cycle the conversion result
is written into the ADDAT register and can be read in the same cycle by an instruction (e.g. MOV
A,ADDAT). If continuous conversion is selected (bit ADM set), the next conversion is started with
the beginning of the machine cycle which follows the write result cycle.
The BSY bit is set at the beginning of the first A/D conversion machine cycle and reset at the
beginning of the write result cycle. If continuous conversion is selected, BSY is again set with the
beginning of the machine cycle which follows the write result cycle. This means that in continuous
conversion mode BSY is not set for a complete machine cycle. Therefore, in continuous conversion
mode it is not recommended to poll the BSY bit using e.g. the JNB instruction.
The interrupt flag IADC is set in the 12th instruction cycle of an A/D conversion. If the A/D converter
interrupt is enabled and the A/D converter interrupt is priorized to be serviced immediately, the first
instruction of the interrupt service routine will be executed in the next machine cycle which follows
the write result cycle. IADC must be reset by software.
Depending on the application, typically there are three methods to handle the A/D conversion in the
C515 :
Depending on the oscillator frequency of the C515 the total time of an A/D conversion is calculated
according the formula given in figure 6-33. Table 6-7 shows some conversion times for typical clock
rates.
Table 6-7
A/D Conversion Times
f
12 MHz
16 MHz
24 MHz
Semiconductor Group
OSC
– Software delay
– Polling BSY bit
– A/D conversion interrupt
The machine cycles of the A/D conversion are counted and the program executes a software
delay (e.g. NOPs) before reading the A/D conversion result in the write result cycle. This is
the fastest method to get the result of an A/D conversion.
The BSY bit is polled and the program waits until BSY=0. Attention : a polling JB instruction
which is two machine cycles long, possibly may not recognize the BSY=0 condition during the
write result cycle in the continuous conversion mode.
After the start of an A/D conversion the A/D converter interrupt is enabled. The result of the
A/D conversion is read in the interrupt service routine. If other C515 interrupts are enabled,
the interrupt latency must be regarded. Therefore, this software method is the slowest method
to get the result of an A/D conversion.
[MHz]
t
166.7
125
83.3
IN
[ns]
Total Conversion Time
t
12
9
6
ADCC
[ms]
6-68
On-Chip Peripheral Components
C515