Z86D99 ZILOG [Zilog, Inc.], Z86D99 Datasheet - Page 74

• Manufacturer Part Number: Z86D99
• Description: Low-Voltage Micro controllers with ADC
• Manufacturer: ZILOG [Zilog, Inc.]

PS003807-1002
Port Configuration Registers (P456CON and P3M)
The port configuration register (described in Table 24) switches the comparator
inputs from digital to analog and allows Ports 4, 5, and/or 6 to be switched from
push/pull active outputs to open drain outputs. In ZiLOG Test Mode, bit 3 of this
register is used to enable the Address Strobe/Data Strobe. Bit 3 is not available in
User Mode.
Table 24. P456CON Register (Group/Bank 0Fh, Register 0)
Port 2 outputs are configured using the P3M Register, shown in Table 25. Bit 0 of
the P3M Register switches Port 2 from push/pull active to open drain outputs. No
other bits in this register are implemented.
Bit
Bit/Field
R/W
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
76______
__5_____
___4____
____3___
_____2__
______1_
_______0
Note: *Do not use the read-modify-write instructions (for example, OR and AND) with this register.
Bits 0, 1, and 2 always read back 1.
Note:
configured as tristate high impedance.
†
For Z86L990/L991, P43 can never be configured as push-pull. After any reset, P43 is
7
Not Used
R/W
0
Bit/Field
Not Used
Comparator 1
Mode
Comparator 2
Mode
Reserved
Port 6 Output
Configuration
Port 5 Output
Configuration
Port 4 Output
Configuration
P
6
R/W
0
R
E
L
5
P51_
Mode
R/W
0
R/W
R/W
R/W
R/W
W
W
W
I
M
Z86D990/Z86D991 OTP and Z86L99X ROM
4
P52_
Mode
R/W
0
Value
0
0
1
0
1
0
1
0
1
1
I
Low-Voltage Microcontrollers with ADC
N
3
Reserved
R/W
0
Description
These bits exist but do not have any
function assigned to them; they are
reserved for future extensions and must
not be used.
Analog (P50, P51 as Inputs)
Digital inputs
Analog comparator inputs (P52, P53
configured as Inputs)
Digital inputs
Push-Pull Active
Open Drain Outputs
Always reads back 1 *
Push-Pull Active
Open Drain Outputs
Always reads back 1 *
Push-Pull Active
Open Drain Outputs
Always reads back 1 *
A
R
Y
2
P6_
Output
W
1
1
P5_
Output
W
1
†
0
P4_
Output
W
1
†
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