Z86D99 ZILOG [Zilog, Inc.], Z86D99 Datasheet - Page 70

• Manufacturer Part Number: Z86D99
• Description: Low-Voltage Micro controllers with ADC
• Manufacturer: ZILOG [Zilog, Inc.]

PS003807-1002
Bit
Bit/Field
R/W
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
7_______
_6______
__5_____
___4____
____3___
_____2__
______1_
_______0
Note:
Interrupt Mask Register
The IMR, as described in Table 21, individually or globally enables the six interrupt
requests. Bit 7 of the IMR is the master enable and must be set before any of the
individual interrupt requests can be recognized. Bit 7 must be set and reset by the
enable interrupts and disable interrupts instructions only. The IMR is automatically
reset during an interrupt service routine and set following the execution of an
Interrupt Return (IRET) instruction.
Table 21. IMR (Group/Bank 0Fh, Register B)
–
–
Bit 7 must be reset by the DI instruction before the contents of
the Interrupt Mask Register or the Interrupt Priority Register are
changed except in the following situations:
Immediately after a hardware reset
Immediately after executing an interrupt service routine and before IMR bit
7 has been set by any instruction
7
Master
R/W
0
Bit/Field
Master
Reserved
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
5
4
3
2
1
0
P
6
Re-
served IRQ5
R/W
0
R
E
L
5
R/W
0
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
I
M
Z86D990/Z86D991 OTP and Z86L99X ROM
4
IRQ4
R/W
0
Value
1
0
1
X
1
0
1
0
1
0
1
0
1
0
1
0
I
Low-Voltage Microcontrollers with ADC
N
A
3
IRQ3
R/W
0
Description
Enable Master Interrupt
Disable Master Interrupt
Always reads 1
No Effect
Enable IRQ
Disable IRQ
Enable IRQ
Disable IRQ
Enable IRQ
Disable IRQ
Enable IRQ
Disable IRQ
Enable IRQ
Disable IRQ
Enable IRQ
Disable IRQ
R
Y
2
IRQ2
R/W
0
5
4
3
2
1
0
5
4
3
2
1
0
1
IRQ1
R/W
0
0
IRQ0
R/W
0
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