Z86D99 ZILOG [Zilog, Inc.], Z86D99 Datasheet - Page 51

• Manufacturer Part Number: Z86D99
• Description: Low-Voltage Micro controllers with ADC
• Manufacturer: ZILOG [Zilog, Inc.]

PS003807-1002
T
trigger
IN
P5
OSC
2
Triggered Input Mode
The T
causes T
then loaded and clocked by the internal timer clock following the first High-to-Low
transition on the T
gle-pass mode, the Enable bit is reset whenever T
ther T
again. In continuous mode, when T
resets the Enable Count bit. Interrupt request IRQ
its end-of-count.
Figure 32. Triggered Clock Mode
Retriggerable Input Mode
The T
load and start counting on every occurrence of a High-to-Low transition on T
(see Figure 32). Interrupt request IRQ
val (determined by T
elapsed since the last High-to-Low transition on T
end-of-count resets the Enable Count bit. Subsequent T
cause T
In continuous mode, counting continues when T
the Enable Count bit. When enabled, each High-to-Low T
IN
IN
IN
1
Retriggerable Input mode (TMR bits D
D
Triggered Input mode (TMR bits D
transitions have no effect on T
1
to load and start counting until software sets the Enable Count bit again.
to start counting as the result of an external event (see Figure 32). T
+2
D
IN
P
input. Subsequent T
1
R
prescaler and counter/timer register initial values) has
E
Edge
trigger
L
I
1
M
TMR
D
is triggered, counting continues until software
Z86D990/Z86D991 OTP and Z86L99X ROM
TMR
D
5
5
5
= 1
1
I
Low-Voltage Microcontrollers with ADC
–D
is generated if the programmed time inter-
until software sets the Enable Count bit
Internal clock
IN
N
4
5
transitions do not affect T
= 11
and D
A
5
+4
and D
1
R
is triggered until software resets
5
IN
4
1
is generated when T
. In single-pass mode, the
set to
reaches its end-of-count. Fur-
Y
4
both set to
IN
IN
1
PRE1
transitions do not
transition causes T
and
0
, respectively)
1
T1
) causes T
1
. In the sin-
1
reaches
IRQ5
IN
IRQ0
1
1
1
to
to
is
44