Z86D99 ZILOG [Zilog, Inc.], Z86D99 Datasheet - Page 28

• Manufacturer Part Number: Z86D99
• Description: Low-Voltage Micro controllers with ADC
• Manufacturer: ZILOG [Zilog, Inc.]

PS003807-1002
Register Function
Stop Mode Recovery
Port 2 SMR Source
Port 5 SMR Source
Notes:
Table 5. Control and Status Register Reset Conditions (Continued)
Power-On Reset
A POR (cold start) always resets the Z8 control and status registers to their default
conditions. A POR sets bit 7 of the Stop Mode Recovery register to 0 to indicate
that a cold start has occurred.
A timer circuit clocked by a dedicated on-board RC oscillator is used for the
Power-On Reset Timer (TPOR) function. The POR time is specified as T
T
cution begins.
The POR delay timer circuit is a one-shot timer triggered by one of three condi-
tions:
•
•
•
Under normal operating conditions, a stop mode recovery event always triggers
the POR delay timer. This delay is necessary to allow the external oscillator time
to stabilize. When using an RC or LC oscillator (with a low Q factor), the shorter
wake-up time means the delay can be eliminated.
Bit 5 of the SMR register selects whether the POR timer delay is used after Stop-
Mode Recovery or is bypassed. If bit 5 =1, then the POR timer delay is used. If bit
5 = 0, then the POR timer delay is bypassed. In this case, the SMR source must
be held in the recovery state for 5 TpC to pass the Reset signal internally.
Watch-Dog Timer (WDT)
The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its
terminal count. When operating in the RUN modes, a WDT reset is functionally
POR
Power Fail to Power OK status including recovery from Low Voltage (V
Standby mode
STOP-Mode Recovery (when bit 5 of the SMR register = 1)
WDT time-out
time allows V
Address
Grp/Bnk Register
†
*This bit is not reset following SMR.
X means this bit is undefined at POR and is not reset following SMR.
**In OTP, the default for P43 is open-drain output at power up; you need to
initialize the P43 data. In the mask part, the P43 output is disabled until it is
configured as output.
0Fh
0Fh
0Fh
This register is not reset following Stop Mode Recovery (SMR).
P
CC
r11
r1
r5
R
and the oscillator circuit to stabilize before instruction exe-
E
L
Symbol
SMR
P2SMR
P5SMR
I
M
Z86D990/Z86D991 OTP and Z86L99X ROM
I
Low-Voltage Microcontrollers with ADC
N
R/W 7
R/W 0
R/W 0
R/W 0
A
R
Reset Value
Y
6
0
0
0
5
1
0
0
4
0
0
0
3
0
0
0
2
0
0
0
POR
1
0
0
0
LV)
.
0
0
0
0
21