LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 476
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LM3S2965-IQN25-A0T
Manufacturer Part Number
LM3S2965-IQN25-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IQN25-A0T.pdf
(542 pages)
- Current page: 476 of 542
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Pulse Width Modulator (PWM)
476
Bit/Field
7:6
9
8
5
4
3
2
1
0
IntCntLoad
TrCntLoad
IntCntZero
TrCntZero
IntCmpBD
IntCmpBU
IntCmpAD
IntCmpAU
reserved
Name
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Reset
0
0
0
0
0
0
0
0
0
Preliminary
Description
When 1, a trigger pulse is output when the counter matches the
PWMnLOAD register.
When 1, a trigger pulse is output when the counter is 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
When 1, an interrupt occurs when the counter matches the comparator B
value and the counter is counting down.
When 1, an interrupt occurs when the counter matches the comparator B
value and the counter is counting up.
When 1, an interrupt occurs when the counter matches the comparator A
value and the counter is counting down.
When 1, an interrupt occurs when the counter matches the comparator A
value and the counter is counting up.
When 1, an interrupt occurs when the counter matches the PWMnLOAD
register.
When 1, an interrupt occurs when the counter is 0.
June 04, 2007
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