LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 179
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LM3S2965-IQN25-A0T
Manufacturer Part Number
LM3S2965-IQN25-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IQN25-A0T.pdf
(542 pages)
- Current page: 179 of 542
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GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x500
Type R/W, reset 0x0000.00FF
June 04, 2007
Reset
Reset
Type
Type
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port
to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO
signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R
register are automatically cleared by hardware.
RO
RO
30
14
0
0
reserved
Name
DRV2
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
Type
27
11
R/W
0
0
RO
RO
RO
26
10
0
0
Reset
0xFF
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n]clears the
corresponding 2-mA enable bit. The change is effective on the second
clock cycle after the write.
RO
RO
24
0
8
0
reserved
R/W
RO
23
0
7
1
R/W
RO
22
0
6
1
R/W
RO
21
0
5
1
R/W
RO
20
0
4
1
DRV2
LM3S2965 Microcontroller
R/W
RO
19
0
3
1
R/W
RO
18
0
2
1
R/W
RO
17
0
1
1
R/W
RO
16
0
0
1
179
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