LM3S2965-IQN25-A0T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IQN25-A0T Datasheet - Page 28
LM3S2965-IQN25-A0T
Manufacturer Part Number
LM3S2965-IQN25-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IQN25-A0T.pdf
(542 pages)
- Current page: 28 of 542
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Architectural Overview
28
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GPIOs
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Power
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Flexible Reset Sources
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Hardware position integrator tracks the encoder position
Velocity capture using built-in timer
Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature
error detection
3-56 GPIOs, depending on configuration
5-V-tolerant input/outputs
Programmable interrupt generation as either edge-triggered or level-sensitive
Bit masking in both read and write operations through address lines
Can initiate an ADC sample sequence
Programmable control for GPIO pad configuration:
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On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
Low-power options on controller: Sleep and Deep-sleep modes
Low-power options for peripherals: software controls shutdown of individual peripherals
User-enabled LDO unregulated voltage detection and automatic reset
3.3-V supply brown-out detection and reporting via interrupt or reset
Power-on reset (POR)
Reset pin assertion
Brown-out (BOR) detector alerts to system power drops
Software reset
Weak pull-up or pull-down resistors
2-mA, 4-mA, and 8-mA pad drive
Slew rate control for the 8-mA drive
Open drain enables
Digital input enables
Preliminary
June 04, 2007
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