MC9S12Q32VFA16 FREESCALE [Freescale Semiconductor, Inc], MC9S12Q32VFA16 Datasheet - Page 452

• Manufacturer Part Number: MC9S12Q32VFA16
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 15 Timer Module (TIM16B6C)
Note: in
15.4.4
The pulse accumulator (PACNT) is a 16-bit counter that can operate in two modes:
Event counter mode — Counting edges of selected polarity on the pulse accumulator input pin, PAI.
Gated time accumulation mode — Counting pulses from a divide-by-64 clock. The PAMOD bit selects the
mode of operation.
The minimum pulse width for the PAI input is greater than two bus clocks.
15.4.5
Clearing the PAMOD bit configures the PACNT for event counter operation. An active edge on the IOC7
pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to
increment the count.
The Pulse Accumulator counter register reflect the number of active input edges on the PACNT input pin
since the last reset.
The PAOVF bit is set when the accumulator rolls over from 0xFFFF to 0x0000. The pulse accumulator
overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests.
452
TC7 event
Figure
Pulse Accumulator
Event Counter Mode
TC7
The PACNT input and timer channel 7 use the same pin IOC7. To use the
IOC7, disconnect it from the output logic by clearing the channel 7 output
mode and output level bits, OM7 and OL7. Also clear the channel 7 output
compare 7 mask bit, OC7M7.
The pulse accumulator counter can operate in event counter mode even
when the timer enable bit, TEN, is clear.
15-29,if PR[2:0] is equal to 0, one prescaler counter equal to one bus clock
prescaler
counter
Figure 15-29. The TCNT cycle diagram under TCRE=1 condition
0
1
MC9S12Q128
Rev 1.10
NOTE
NOTE
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TC7-1
TC7 event
1 bus
clock
TC7
Freescale Semiconductor
0