MC9S12Q32VFA16 FREESCALE [Freescale Semiconductor, Inc], MC9S12Q32VFA16 Datasheet - Page 448

• Manufacturer Part Number: MC9S12Q32VFA16
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 15 Timer Module (TIM16B6C)
For the description of PACLK please refer
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an
input clock to the timer counter. The change from one selected clock to the other happens immediately
after these bits are written.
15.3.2.16 Pulse Accumulator Flag Register (PAFLG)
Read: Anytime
Write: Anytime
When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags
in the PAFLG register.
448
Module Base + 0x0021
Reset
W
R
0
0
7
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the 64 clock is generated by the timer prescaler.
PAMOD
CLK1
Unimplemented or Reserved
0
0
1
1
0
0
1
1
Figure 15-25. Pulse Accumulator Flag Register (PAFLG)
0
0
6
PEDGE
CLK0
0
1
0
1
0
1
0
1
Table 15-20. Timer Clock Selection
0
0
5
Table 15-19. Pin Action
Use PACLK/65536 as timer counter clock frequency
Use PACLK/256 as timer counter clock frequency
Figure
Use timer prescaler clock as timer counter clock
Div. by 64 clock enabled with pin high level
Use PACLK as input to timer counter clock
Div. by 64 clock enabled with pin low level
MC9S12Q128
Rev 1.10
NOTE
15-24.
0
0
4
Timer Clock
Falling edge
Rising edge
Pin Action
0
0
3
0
0
2
PAOVF
Freescale Semiconductor
0
1
PAIF
0
0