MC9S12Q32VFA16 FREESCALE [Freescale Semiconductor, Inc], MC9S12Q32VFA16 Datasheet - Page 449

• Manufacturer Part Number: MC9S12Q32VFA16
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

15.3.2.17 Pulse Accumulators Count Registers (PACNT)
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on its input pin since the last reset.
When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word.
Freescale Semiconductor
Module Base + 0x0022
Module Base + 0x0023
PAOVF
Reset
Reset
Field
PAIF
1
0
W
W
R
R
PACNT15
PACNT7
Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000.
This bit is cleared automatically by a write to the PAFLG register with bit 1 set.
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IOC7 input pin triggers PAIF.
This bit is cleared by a write to the PAFLG register with bit 0 set.
Any access to the PACNT register will clear all the flags in this register when TFFCA bit in register TSCR(0x0006)
is set.
15
0
0
7
edge on the pulse accumulator input pin may miss the last count because the
input has to be synchronized with the bus clock first.
Reading the pulse accumulator counter registers immediately after an active
Figure 15-26. Pulse Accumulator Count Register High (PACNTH)
Figure 15-27. Pulse Accumulator Count Register Low (PACNTL)
PACNT14
PACNT6
14
0
0
6
Table 15-21. PAFLG Field Descriptions
PACNT13
PACNT5
13
0
0
5
PACNT12
MC9S12Q128
PACNT4
Rev 1.10
NOTE
12
0
0
4
Description
PACNT11
PACNT3
11
0
0
3
PACNT10
PACNT2
10
0
0
2
Chapter 15 Timer Module (TIM16B6C)
PACNT9
PACNT1
0
0
9
1
PACNT8
PACNT0
0
0
0
0
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