COP8SBR9 NSC [National Semiconductor], COP8SBR9 Datasheet - Page 29

• Manufacturer Part Number: COP8SBR9
• Description: 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout
• Manufacturer: NSC [National Semiconductor]

11.0 In-System Programming
11.4 MANEUVERING BACK AND FORTH BETWEEN
FLASH MEMORY AND BOOT ROM
When using ISP, at some point, it will be necessary to
maneuver between the flash program memory and the Boot
ROM, even when using customized ISP routines. This is
because it’s not possible to execute from the flash program
memory while it’s being programmed.
Two instructions are available to perform the jumping back
and forth: Jump to Boot (JSRB) and Return to Flash (RETF).
The JSRB instruction is used to jump from flash memory to
Boot ROM, and the RETF is used to return from the Boot
ROM back to the flash program memory. See 19.0 Instruc-
tion Set for specific details on the operation of these instruc-
tions.
The JSRB instruction must be used in conjunction with the
Key register. This is to prevent jumping to the Boot ROM in
the event of run-away software. For the JSRB instruction to
actually jump to the Boot ROM, the Key bit must be set. This
is done by writing the value shown in Table 9 to the Key
register. The Key is a 6 bit key and if the key matches, the
KEY bit will be set for 8 instruction cycles. The JSRB instruc-
tion must be executed while the KEY bit is set. If the KEY
does not match, then the KEY bit will not be set and the
JSRB will jump to the specified location in the flash memory.
In emulation mode, if a breakpoint is encountered while the
KEY is set, the counter that counts the instruction cycles will
be frozen until the breakpoint condition is cleared. If an
interrupt occurs while the key is set, the key will expire
before interrupt service is complete. It is recommended that
the software globally disable interrupts before setting the
key. The Key register is a memory mapped register. Its
format when writing is shown in Table 9. In normal operation,
it is not necessary to test the KEY bit before using the JSRB
instruction. The additional instructions required to test the
key may cause the key to time-out before the JSRB can be
executed.
Bits 7–2: Key value that must be written to set the KEY bit.
Bits 1–0: Don’t care.
11.5 FORCED EXECUTION FROM BOOT ROM
When the user is developing a customized ISP routine, code
lockups due to software errors may be encountered. The
normal, and preferred, method to recover from these condi-
tions is to reprogram the device with the corrected code by
either an external parallel programmer or the emulation
tools. As a last resort, when this equipment is not available,
there is a hardware method to get out of these lockups and
force execution from the Boot ROM MICROWIRE/PLUS
routine. The customer will then be able to erase the Flash
Memory code and start over.
The method to force this condition is to drive the G6 pin to
high voltage (2 x V
condition on G6 must not be applied before V
stable, and must be held for at least 3 instruction cycles
longer than Reset is active. This special condition will by-
pass checking the state of the Flex bit in the Option Register
(Continued)
Bit 7
1
Bit 6
0
TABLE 9. KEY Register Write Format
Bit 5
0
CC
) and activate Reset. The high voltage
KEY When Writing
Bit 4
1
Bit 3
1
Bit 2
0
CC
Bit 1
X
is valid and
Bit 0
X
29
and will start execution from location 0000 in the Boot ROM.
In this state, the user can input the appropriate commands,
using MICROWIRE/PLUS, to erase the flash program
memory and reprogram it. If the device is subsequently reset
before the Flex bit has been erased by specific Page Erase
or Mass Erase ISP commands, execution will start from
location 0000 in the Flash program memory. The high volt-
age (2 x V
Security bit in the Option Register. The Security bit, if set,
can only be erased by a Mass Erase of the entire contents of
the Flash Memory unless under the control of User ISP
routines in the Application Program.
While the G6 pin is at high voltage, the Load Clock will be
output onto G5, which will look like an SK clock to the
MICROWIRE/PLUS routine executing in slave mode. How-
ever, when G6 is at high voltage, the G6 input will also look
like a logic 1. The MICROWIRE/PLUS routine in Boot ROM
monitors the G6 input, waits for it to go low, debounces it,
and then enables the ISP routine. CAUTION: The Load clock
on G5 could be in conflict with the user’s external SK. It is up
to the user to resolve this conflict, as this condition is con-
sidered a minor issue that’s only encountered during soft-
ware development. The user should also be cautious of
the high voltage applied to the G6 pin. This high voltage
could damage other circuitry connected to the G6 pin
(e.g. the parallel port of a PC). The user may wish to
disconnect other circuitry while G6 is connected to the high
voltage.
V
to G6.
The correct sequence to be used to force execution from
Boot ROM is :
1. Disconnect G6 from the source of data for MICROWIRE/
2. Apply V
3. Pull RESET Low.
4. After V
5. Pull RESET High.
6. After a delay of at least three instruction cycles, remove
FIGURE 14. Circuit Diagram for Implementing the 2 x
CC
PLUS ISP.
2 x V
time of the high voltage on G6 is slower than the mini-
mum in the Electrical Specifications. Figure 14 shows a
possible circuit dliagram for implementing the 2 x V
Be aware of the typical input current on the G6 pin when
the high voltage is applied. The resistor used in the RC
network, and the high voltage used, should be chosen to
keep the high voltage at the G6 pin between 2 x V
V
the high voltage from G6.
must be valid and stable before high voltage is applied
CC
+7V.
CC
CC
CC
CC
and V
) on G6 will not erase either the Flex or the
is valid and stable, connect a voltage between
to the device.
CC
+7V to the G6 pin. Ensure that the rise
V
CC
www.national.com
10138966
CC
and
CC
.