COP8SBR9 NSC [National Semiconductor], COP8SBR9 Datasheet - Page 14

• Manufacturer Part Number: COP8SBR9
• Description: 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout
• Manufacturer: NSC [National Semiconductor]

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Operating Voltage
Power Supply Rise Time
Power Supply Ripple (Note 2)
Supply Current (Note 3)
High Speed Mode
Dual Clock Mode
Low Speed Mode
HALT Current with BOR Disabled (Note 4)
Idle Current (Note 3)
High Speed Mode
8.0 Electrical Characteristics
AC Electrical Characteristics (−40˚C ≤ T
Output Pulse Width
USART Bit Time when using External
CKX
USART CKX Frequency when being
Driven by Internal Baud Rate Generator
Reset Pulse Width
t
Note 2: Maximum rate of voltage change must be
Note 3: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V
and outputs driven low but not connected to a load.
Note 4: The HALT mode will stop CKI from oscillating. Measurement of I
and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a load; all inputs tied to V
monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
biased at voltages
be limited to
Note 6: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 t
Note 7: Absolute Maximum Ratings should not be exceeded.
Note 8: V
DC Electrical Characteristics (−40˚C ≤ T
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
CKI = 10 MHz
CKI = 3.33 MHz
CKI = 10 MHz, Low Speed OSC = 32 kHz
CKI = 3.33 MHz, Low Speed OSC = 32 kHz
Low Speed OSC = 32 kHz
High Speed Mode
Dual Clock Mode
Low Speed Mode
CKI = 10 MHz
C
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Timer 1 Input High Time
Timer 1 Input Low Time
Timer 2, 3 Input High Time (Note 6)
Timer 2, 3 Input Low Time (Note 6)
Timer 2, 3 Output High Time
Timer 2, 3 Output Low Time
= instruction cycle time.
CC
<
must be valid and stable before G6 is raised to a high voltage.
14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.
>
Parameter
V
CC
Parameter
(the pins do not have source current when biased at a voltage below V
<
0.5 V/ms.
(Continued)
Peak-to-Peak
V
V
V
V
V
V
V
Speed OSC = 32 kHz
V
Speed OSC = 32 kHz
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
Conditions
= 5.5V, t
= 4.5V, t
= 5.5V, t
= 4.5V, t
= 5.5V
= 5.5V, CKI = 0 MHz
= 5.5V, CKI = 0 MHz, Low
= 5.5V, CKI = 0 MHz, Low
= 5.5V, t
DD
HALT is done with device neither sourcing nor sinking current; with L. A. B, C, E, F, G0,
Conditions
14
C
C
C
C
C
= 0.5 µs
= 1.5 µs
= 0.5 µs
= 1.5 µs
= 0.5 µs
A
A
≤ +85˚C)
≤ +125˚C)
CC
). These two pins will not latch up. The voltage at the pins must
periods
6 CKI
Min
150
150
1
1
1
1
1
>
(Continued)
V
CC
Min
and the pins will have sink current to V
4.5
10
Typ
65
Typ
<
<
<
C
4
9
9
.
Max
CC
2
50 x 10
; A/D converter and clock
0.1 V
Max
14.5
14.5
110
5.5
2.7
40
50
50
7
7
CC
6
MCLK or t
MCLK or t
Units
MHz
CC
ns
ns
µs
t
t
t
Units
C
C
C
mA
mA
mA
mA
mA
µA
µA
µA
µA
ns
when
V
V
CC
C
C