MCF5329DS ANALOGICTECH [Advanced Analogic Technologies], MCF5329DS Datasheet - Page 25

• Manufacturer Part Number: MCF5329DS
• Description: MCF5329 ColdFire Microprocessor Data Sheet
• Manufacturer: ANALOGICTECH [Advanced Analogic Technologies]

Symbol
5.8
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports
either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
5.8.1
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read
cycles. The device’s SDRAM controller is a DDR controller that has an SDR mode. Because it is designed
to support DDR, a DQS pulse must still be supplied to device for each data beat of an SDR read. Te
processor accomplishes this by asserting a signal named SD_DQS during read cycles. Care must be taken
during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal
and its usage.
Freescale Semiconductor
SD1
SD2
SD3
Frequency of Operation
Clock Period
Clock Skew
Pulse Width High
SDRAM Bus
BE/BWEn
SDR SDRAM AC Timing Characteristics
FB_CLK
FB_CSn
D[31:0]
A[23:0]
R/W
OE
TS
TA
Characteristic
MCF5329 ColdFire
FB1
FB2
Table 11. SDR Timing Specifications
Figure 11. Flexbus Write Timing
®
Microprocessor Data Sheet, Rev. 0.1
FB6
Preliminary
Symbol
t
t
t
SDCKH
FB7
SDCK
SDSK
TBD
12.5
0.45
Min
FB3
FB3
—
Preliminary Electrical Characteristics
Max
TBD
TBD
0.55
80
SD_CLK
Unit
Mhz
ns
Notes
1
2
3
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