ST7FMC1K2TC STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2TC Datasheet - Page 175
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ST7FMC1K2TC
Manufacturer Part Number
ST7FMC1K2TC
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST7FMC1K2TC.pdf
(308 pages)
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MOTOR CONTROLLER (Cont’d)
When using hardware commutation C
quence of events needed is C
Z events and the value written in the registers are
checked at different times.
If SDM bit is set, meaning simulated demagnetisa-
tion, a value must be written in the MDREG regis-
ter to generate the simulated demagnetisation.
This value must be written after the C (either C
C
tion.
If SZ bit is set, meaning simulated zero-crossing
event, a value must be written in the MZREG reg-
ister to generate the simulated zero-crossing. This
value must be written after the D event (D
preceding the simulated zero-crossing.
When using simulated commutation (C
sult of the 8*8 hardware multiplication of the delay
manager is not taken in account and must be over-
written if the SC bit has been set in a Z event inter-
rupt and the sequence of events is broken mean-
ing that several consecutive simulated commuta-
tions can be implemented.
As soon as the SC bit is set in the MCRC register,
the system won’t necessarily expect a D event af-
ter a C event. This can be used for an application
in sensor mode with only one Hall Effect sensor for
example.
Be careful that the D and Z events are not ignored
by the peripheral, this means that for example if a
H
) event preceding the simulated demagnetisa-
H
then D and finally
H
S
, the se-
), the re-
H
or D
s
or
S
)
Z event occurs, the MTIM timer is reset. In Simu-
lated Commutation mode, the sequence D -> Z is
expected, and this order must be repected.
As the sequence of events may not be the same
when using simulated commutation, as soon as
the SC bit is set, the capture/compare feature and
protection on MCOMP register is reestablished
only after a write to the MCOMP register. This
means that as soon as the SC bit is set, if no write
access is done to the MCOMP register, no com-
mutation event will be generated, whatever the
value of MCOMP compared to MTIM at the time
SC is set. This does not depend on the running
mode: switched or autoswitched mode (SWA bit).
If software commutation event is used with a nor-
mal sequence of events C-->D-->Z, it is recom-
mended to write the MCOMP register during the Z
interrupt routine to avoid any spurious comparison
as several consecutive C
ed.
Note that two different simulated events can be
used in the same step (like D
Note also that for more precision, it is recommend-
ed to use the value captured from the preceding
hardware event to compute the value used to gen-
erate simulated events.
Figure
of simulated event generation.
95,
Figure 96
and
s
Figure 97
events can be generat-
ST7MC1/ST7MC2
S
followed by Z
shows details
175/308
S
).
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