ST7FLITE29 STMICROELECTRONICS [STMicroelectronics], ST7FLITE29 Datasheet - Page 67

• Manufacturer Part Number: ST7FLITE29
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

LITE TIMER (Cont’d)
– The opcode for the HALT instruction is 0x8E. To
– As the HALT instruction clears the I bit in the CC
11.3.4 Low Power Modes
11.3.5 Interrupts
Note: The TBxF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
They generate an interrupt if the enable bit is set in
the LTCSR1 or LTCSR2 register and the interrupt
mask in the CC register is reset (RIM instruction).
Mode
SLOW
WAIT
ACTIVE-HALT No effect on Lite timer
HALT
Timebase 1
Event
Timebase 2
Event
IC Event
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
Interrupt
Event
Event
TB1F
TB2F
Flag
ICF
Description
No effect on Lite timer
(this peripheral is driven directly
by f
No effect on Lite timer
Lite timer stops counting
Control
Enable
TB1IE
TB2IE
OSC
ICIE
Bit
/32)
from
Wait
Exit
Yes
Yes
Yes
Active
from
Exit
Halt
Yes
No
No
from
Halt
Exit
No
No
No
11.3.6 Register Description
LITE TIMER CONTROL/STATUS REGISTER 2
(LTCSR2)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = TB2IE Timebase 2 Interrupt enable .
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
Bit 0 = TB2F Timebase 2 Interrupt Flag .
This bit is set by hardware and cleared by software
reading the LTCSR register. Writing to this bit has
no effect.
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
LITE
(LTARR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = AR[7:0] Counter 2 Reload Value.
These bits register is read/write by software. The
LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
AR7
7
0
7
AR7
TIMER
0
AR7
0
AUTORELOAD
AR7
0
AR3
0
AR2
0
ST7LITE2
TB2IE
REGISTER
AR1
67/131
TB2F
AR0
0
0
1