STM32F101X6_08 STMICROELECTRONICS [STMicroelectronics], STM32F101X6_08 Datasheet - Page 10

• Manufacturer Part Number: STM32F101X6_08
• Description: Access line, advanced ARM-based 32-bit MCU with Flash memory, six 16-bit timers, ADC and seven communication interfaces
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Description
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Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is
monitored for failure. During such a scenario, it is disabled and software interrupt
management follows. Similarly, full interrupt management of the PLL clock entry is available
when necessary (for example on failure of an indirectly used external crystal, resonator or
oscillator).
Several prescalers allow the configuration of the AHB frequency, the High Speed APB
(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 36 MHz. See
Boot modes
At startup, boot pins are used to select one of five boot options:
●
●
●
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Power supply schemes
●
●
●
For more details on how to connect power pins, refer to
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.
The device features an embedded Programmable voltage detector (PVD) that monitors the
V
when V
interrupt service routine can then generate a warning message and/or put the MCU into a
safe state. The PVD is enabled by software.
Refer to
V
DD
POR/PDR
Boot from User Flash
Boot from System Memory
Boot from SRAM
V
Provided externally through V
V
and PLL. In V
V
V
registers (through power switch) when V
power supply and compares it to the V
DD
SSA
DDA
BAT
DD
Table 9: Embedded reset and power control block characteristics
= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
, V
= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
and V
and V
drops below the V
DDA
PVD
SSA
= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
DD
.
must be connected to V
range (ADC is limited at 2.4 V).
DD
is below a specified threshold, V
PVD
and/or when V
Figure 2
DD
pins.
for details on the clock tree.
PVD
DD
DD
threshold. An interrupt can be generated
and V
DD
is not present.
is higher than the V
SS
Figure 10: Power supply
, respectively.
POR/PDR
, without the need for an
PVD
for the values of
threshold. The
STM32F101xx
scheme.