STR910FAZ32H6T STMICROELECTRONICS [STMicroelectronics], STR910FAZ32H6T Datasheet - Page 21

• Manufacturer Part Number: STR910FAZ32H6T
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STR91xFAx32 STR91xFAx42 STR91xFAx44
3.10.2
3.10.3
3.10.4
3.10.5
Figure 2.
Reference clock (RCLK)
The main clock (f
(RCLK) for the ARM core and all the peripherals. The RCLK provides the divided clock for
the ARM core, and feeds the dividers for the AHB, APB, External Memory Interface, and
FMI units.
AHB clock (HCLK)
The RCLK can be divided by 1, 2 or 4 to generate the AHB clock. The AHB clock is the bus
clock for the AHB bus and all bus transfers are synchronized to this clock. The maximum
HCLK frequency is 96 MHz.
APB clock (PCLK)
The RCLK can be divided by 1, 2, 4 or 8 to generate the APB clock. The APB clock is the
bus clock for the APB bus and all bus transfers are synchronized to this clock. Many of the
peripherals that are connected to the AHB bus also use the PCLK as the source for external
bus data transfers. The maximum PCLK frequency is 48 MHz.
Flash memory interface clock (FMICLK)
The FMICLK clock is an internal clock derived from RCLK, defaulting to RCLK frequency at
power up. The clock can be optionally divided by 2. The FMICLK determines the bus
bandwidth between the ARM core and the Flash memory. Typically, codes in the Flash
memory can be fetched one word per FMICLK clock in burst mode. The maximum FMICLK
frequency is 96MHz.
EXTCLK_T2T3
EXTCLK_T0T1
USB_CLK48M
MII_PHYCLK
X1_CPU
X1_RTC
X1_CPU
X2_RTC
JRTCLK
4-25MHz
Clock control
32.768 kHz
48MHz
25MHz
MSTR
Main
OSC
RTC
OSC
) can be divided to operate at a slower frequency reference clock
External clock
Timer 2 & 3
External clock
Timer 0 & 1
f
OSC
32.768 kHz
f
RTC
RTCSEL
PHYSEL
PLL
f
PLL
Master CLK
f
MSTR
(1,2,4,8,16,1024)
1/2
1/2
RCLK
DIV
To USB
To UART
BRCLK
USBCLK
Functional overview
RCLK
1/2
1/2
AHB DIV
APB DIV)
(1,2,4)
(1,2,4,8)
CPUCLK
FMICLK
EMI_BCLK
PCLK
HCLK
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