ZLF645 MAXIM [Maxim Integrated Products], ZLF645 Datasheet - Page 152

• Manufacturer Part Number: ZLF645
• Description: Flash MCUs with Learning Amplification
• Manufacturer: MAXIM [Maxim Integrated Products]

19-4572; Rev 0; 4/09
Note:
Stop Mode Recovery Interrupt
Stop Mode Recovery Event Sources
SMR Register Events
SMR[5] must be set to 1 if using a crystal or resonator clock source. The T
allows the clock source to stabilize before executing instructions.
Software can set register bit SMR4[4] = 1 to enable routing of Stop Mode Recovery events
to IRQ1 and to Port 3, Pin 3. In this configuration, if an IRQ1 interrupt occurs, register bit
P3[3] = 0 indicates that a Stop Mode Recovery event is occurring.
Any Port 2 or Port 3 input pin can be configured to generate a Stop Mode Recovery event,
either individually or in various logical combinations. The ZLF645 MCU provides the
following registers for Stop Mode Recovery source configuration and status:
•
•
•
•
•
A Stop Mode Recovery event occurs if any of the sources defined in the SMR, SMR1,
SMR2, and SMR3 registers are active.
The SMR register function is similar to the standard Stop Mode Recovery feature used in
previous Z8
event modes, as displayed in
is compared to the state of SMR[6]; when they are the same, a Stop Mode Recovery event
is generated. If SMR[4:2]=000, no event source is selected by SMR.
The state SMR[4:2]=001 is reserved and selects no event in this device. The logic config-
ured by the SMR register ignores any port pins that are configured as output or selected as
source pins in registers SMR1 or SMR3. The SMR register is summarized in
page 146.
SMR Register—Selects one Port 3, Pin 1–3 pin state or one of three Port 2 pin logical
combinations to generate an event when a defined 0 or 1 level occurs.
SMR1 Register—Configures one or more Port 2 input pins (0–7) to latch the latest
read or write value and generate an event when the pin state changes.
SMR2 Register—Selects one of seven Port 2 and 3 pin logical combinations to
generate an event when a defined 0 or 1 level occurs.
SMR3 Register—Configures one or more Port 3 input pins (0–3) to latch the latest
read or write value and generates an event when the pin state changes.
SMR4 Register—Enables routing of SMR events to IRQ1. Indicates whether port data
has been latched for SMR1 or SMR3 event monitoring, and whether the latch was on
a port read or write.
®
CPU-compatible parts. Register bits SMR[4:2] are set to select one of six
Figure 44
on page 145. The output of the corresponding logic
ZLF645 Series Flash MCUs
Reset/Stop Mode Recovery Status
Product Specification
Table 69
POR
delay
on
144