LPC2888FET180/01 NXP [NXP Semiconductors], LPC2888FET180/01 Datasheet - Page 20

• Manufacturer Part Number: LPC2888FET180/01
• Description: 16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC2880_LPC2888_3
Preliminary data sheet
6.14.1 Features
6.15.1 Features
6.14 UART and IrDA
6.15 I
The LPC2880/2888 contains one UART with baud rate generator and IrDA support.
The LPC2880/2888 I
master Transmit mode, master Receive mode, slave Transmit mode and slave Receive
mode. The interface complies with the entire I
power off to the LPC2880/2888 without causing a problem with other devices on the same
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C-bus.
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C-bus interface
The GPDMA supports a subset of the flow control signals supported by ARM DMA
channels, specifically ‘single’ but not ‘burst’ operation.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers.
Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
Rotating channel priority. Each DMA channel has equal opportunity to perform
transfers.
The GPDMA is one of three AHB masters in the LPC2880/2888, the others being the
ARM7 processor and the USB interface.
Incrementing or non-incrementing addressing for source and destination.
Supports 8 bit, 16 bit, and 32 bit wide transactions.
GPDMA channels can be programmed to swap data between big- and little-endian
formats during a transfer.
An interrupt to the processor can be generated on DMA completion, when a DMA
channel is halfway to completion, or when a DMA error has occurred.
32-Byte Receive and Transmit FIFOs.
Register locations conform to the 16C650 industry standard.
Receiver FIFO trigger points at 1 B, 16 B, 24 B, and 28 B.
Built-in baud rate generator.
CGU generates UART clock including fractional divider capability.
Auto baud capability.
Optional hardware flow control.
IrDA mode for infrared communication.
Standard I
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Programmable clock allows adjustment of I
Bidirectional data transfer between masters and slaves.
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C-bus interface, configurable as Master, Slave, or Master/Slave.
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C-bus interface is byte oriented and has four operating modes:
16/32-bit ARM microcontrollers with external memory interface
Rev. 03 — 17 April 2008
2
C-bus specification , and allows turning
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C-bus transfer rates.
LPC2880; LPC2888
© NXP B.V. 2008. All rights reserved.
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