LPC2888FET180/01 NXP [NXP Semiconductors], LPC2888FET180/01 Datasheet - Page 15

• Manufacturer Part Number: LPC2888FET180/01
• Description: 16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC2880_LPC2888_3
Preliminary data sheet
6.3.1 Cache operation
6.3.2 Features
6.3 Cache
6.4 Flash memory and programming
The CPU of the LPC2880/2888 has been extended with a 2-way set-associative cache.
The cache is 8 kB in size and can store both data and instruction code.
If code that is being executed is present in the cache from a previous execution, the CPU
will not experience code fetch waits. Similarly, if requested data is present in the cache,
the CPU will not experience a data access wait.
The trade-off of introducing this cache is that each AHB access that bypasses the cache
will have an extra wait state inserted. Therefore it is advisable that both instruction caching
and data caching are turned on for most regions of on and off-chip memory.
The cache works as follows, for each page for which it is enabled:
The cache can be set to data-only, instruction-only or combined (unified) caching. The
cache has 16 configurable pages, each 2 MB in range. The pages occupy the bottom
32 MB of the memory map. The virtual address and enable/disable status is configurable
for each page.
The LPC2888 incorporates 1 MB of flash memory, while the LPC2880 is a flash-less
device. The flash memory of the LPC2888 may be used for both code and data storage.
Programming of the flash memory may be accomplished in several ways. It may be
programmed In System via the USB port. The application program may also erase and/or
program the flash while the application is running, allowing a great degree of flexibility for
data storage, field firmware upgrades, etc.
•
•
•
•
•
•
•
•
•
If data is read and is not in the cache (a cache miss), a line of eight 32-bit words is
read from the AHB bus. The CPU waits until this process is complete.
If data is read and is found in the cache (a cache hit), data is read from cache with
zero wait states.
If data is written, and the location is not in the cache (a cache miss), the data is written
directly to memory.
If data is written, and the location is in the cache because this location has been read
before (a cache hit), the data is written into the cache with zero wait states, and the
cache line is marked as ‘dirty’.
If a ‘dirty’ cache line is about to be discarded because of a cache miss (the cache line
needs to be reused for a different memory region), the old line is written back to
memory (a cache-line flush).
8 kB, 2-way set-associative cache.
May be used as both an instruction and data cache.
Zero wait states for a cache hit.
16 configurable pages, each 2 MB in range.
16/32-bit ARM microcontrollers with external memory interface
Rev. 03 — 17 April 2008
LPC2880; LPC2888
© NXP B.V. 2008. All rights reserved.
15 of 43