DSPIC30F6012 MICROCHIP [Microchip Technology], DSPIC30F6012 Datasheet - Page 134

• Manufacturer Part Number: DSPIC30F6012
• Description: High-Performance, 16-Bit Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F6011/6012/6013/6014
18.3.18
The SLOT<3:0> status bits in the DCISTAT SFR indi-
cate the current active time slot. These bits will corre-
spond to the value of the frame sync generator counter.
The user may poll these status bits in software when a
DCI interrupt occurs to determine what time slot data
was last received and which time slot data should be
loaded into the TXBUF registers.
18.3.19
The CSDOM control bit controls the behavior of the
CSDO pin during unused transmit slots. A given trans-
mit time slot is unused if it’s corresponding TSEx bit in
the TSCON SFR is cleared.
If the CSDOM bit is cleared (default), the CSDO pin will
be low during unused time slot periods. This mode will
be used when there are only two devices attached to
the serial bus.
If the CSDOM bit is set, the CSDO pin will be tri-stated
during unused time slot periods. This mode allows mul-
tiple devices to share the same CSDO line in a multi-
channel application. Each device on the CSDO line is
configured so that it will only transmit data during
specific time slots. No two devices will transmit data
during the same time slot.
18.3.20
Digital Loopback mode is enabled by setting the
DLOOP control bit in the DCISTAT SFR. When the
DLOOP bit is set, the module internally connects the
CSDO signal to CSDI. The actual data input on the
CSDI I/O pin will be ignored in Digital Loopback mode.
18.3.21
When an underflow occurs, one of two actions may
occur depending on the state of the Underflow mode
(UNFM) control bit in the DCICON1 SFR. If the UNFM
bit is cleared (default), the module will transmit ‘0’s on
the CSDO pin during the active time slot for the buffer
location. In this Operating mode, the Codec device
attached to the DCI module will simply be fed digital
‘silence’. If the UNFM control bit is set, the module will
transmit the last data written to the buffer location. This
Operating mode permits the user to send continuous
data to the Codec device without consuming CPU
overhead.
18.4
The frequency of DCI module interrupts is dependent
on the BLEN<1:0> control bits in the DCICON2 SFR.
An interrupt to the CPU is generated each time the set
buffer length has been reached and a shadow register
transfer takes place. A shadow register transfer is
defined as the time when the previously written TXBUF
values are transferred to the transmit shadow registers
and new received values in the receive shadow
registers are transferred into the RXBUF registers.
DS70117F-page 132
DCI Module Interrupts
SLOT STATUS BITS
CSDO MODE BIT
DIGITAL LOOPBACK MODE
UNDERFLOW MODE CONTROL BIT
18.5
18.5.1
The DCI module has the ability to operate while in
Sleep mode and wake the CPU when the CSCK signal
is supplied by an external device (CSCKD = 1). The
DCI module will generate an asynchronous interrupt
when a DCI buffer transfer has completed and the CPU
is in Sleep mode.
18.5.2
If the DCISIDL control bit is cleared (default), the mod-
ule will continue to operate normally even in Idle mode.
If the DCISIDL bit is set, the module will halt when Idle
mode is asserted.
18.6
The AC-Link protocol is a 256-bit frame with one 16-bit
data slot, followed by twelve 20-bit data slots. The DCI
module has two Operating modes for the AC-Link pro-
tocol. These Operating modes are selected by the
COFSM<1:0> control bits in the DCICON1 SFR. The
first AC-Link mode is called ‘16-bit AC-Link mode’ and
is selected by setting COFSM<1:0> = 10. The second
AC-Link mode is called ‘20-bit AC-Link mode’ and is
selected by setting COFSM<1:0> = 11.
18.6.1
In the 16-bit AC-Link mode, data word lengths are
restricted to 16 bits. Note that this restriction only
affects the 20-bit data time slots of the AC-Link proto-
col. For received time slots, the incoming data is simply
truncated to 16 bits. For outgoing time slots, the 4 LSbs
of the data word are set to ‘0’ by the module. This trun-
cation of the time slots limits the A/D and DAC data to
16 bits but permits proper data alignment in the TXBUF
and RXBUF registers. Each RXBUF and TXBUF regis-
ter will contain one data time slot value.
18.6.2
The 20-bit AC-Link mode allows all bits in the data time
slots to be transmitted and received but does not main-
tain data alignment in the TXBUF and RXBUF
registers.
The 20-bit AC-Link mode functions similar to the Multi-
Channel mode of the DCI module, except for the duty
cycle of the frame synchronization signal. The AC-Link
frame synchronization signal should remain high for 16
CSCK cycles and should be low for the following
240 cycles.
DCI Module Operation During CPU
Sleep and Idle Modes
AC-Link Mode Operation
DCI MODULE OPERATION DURING
CPU SLEEP MODE
DCI MODULE OPERATION DURING
CPU IDLE MODE
16-BIT AC-LINK MODE
20-BIT AC-LINK MODE
© 2006 Microchip Technology Inc.