LPC2292FBD144/00 PHILIPS [NXP Semiconductors], LPC2292FBD144/00 Datasheet - Page 17

• Manufacturer Part Number: LPC2292FBD144/00
• Description: 16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with CAN, 10-bit ADC and external memory interface
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
LPC2292_2294_6
Product data sheet
6.5.1 Interrupt sources
6.5 Interrupt controller
The VIC accepts all of the interrupt request inputs and categorizes them as Fast Interrupt
Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by
programmable settings. The programmable assignment scheme means that priorities of
interrupts from the various peripherals can be dynamically assigned and adjusted.
FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classified as FIQ, because then
the FIQ service routine can simply start dealing with that device. But if more than one
request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC
that identifies which FIQ source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.
Table 5
one interrupt line connected to the VIC, but may have several internal interrupt flags.
Individual interrupt flags may also represent more than one interrupt source.
Table 5.
Block
WDT
-
ARM Core
ARM Core
Timer 0
Timer 1
UART0
lists the interrupt sources for each peripheral function. Each peripheral device has
Interrupt sources
Flag(s)
Watchdog Interrupt (WDINT)
Reserved for software interrupts only
EmbeddedICE, DbgCommRx
EmbeddedICE, DbgCommTx
Match 0 to 3 (MR0, MR1, MR2, MR3)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
Match 0 to 3 (MR0, MR1, MR2, MR3)
Capture 0 to 3 (CR0, CR1, CR2, CR3)
RX Line Status (RLS)
Transmit Holding Register Empty (THRE)
RX Data Available (RDA)
Character Time-out Indicator (CTI)
Rev. 06 — 10 December 2007
16/32-bit ARM microcontrollers with external memory interface
LPC2292/LPC2294
© NXP B.V. 2007. All rights reserved.
VIC channel #
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