AT32UC3B0512-A2UES ATMEL [ATMEL Corporation], AT32UC3B0512-A2UES Datasheet - Page 68

• Manufacturer Part Number: AT32UC3B0512-A2UES
• Description: 32-bit AVR Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

12.1.2.4
12.1.2.5
12.1.2.6
12.1.2.7
SSC
USB
ADC
PDCA
1. Additional delay on TD output
2. TF output is not correct
3. Frame Synchro and Frame Synchro Data are delayed by one clock cycle.
1. For isochronous pipe, the INTFRQ is irrelevant
1. Sleep Mode activation needs additional A to D conversion
1. Wrong PDCA behavior when using two PDCA channels with the same PID
If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis-
abled, this will lead to an increased power consumption in VDDIO.
Fix/Workaround
Disable the OSC0 through the Power Manager (PM) before going to any sleep mode where
the OSC0 is disabled, or pull down or up XIN0 and XOUT0 with 1Mohm resistor.
A delay from 2 to 3 system clock cycles is added to TD output when:
TCMR.START = Receive Start,
TCMR.STTDLY = more than ZERO,
RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge,
RFMR.FSOS = None (input).
Fix/Workaround
None.
TF output is not correct (at least emitted one serial clock cycle later than expected) when:
TFMR.FSOS = Driven Low during data transfer/ Driven High during data transfer
TCMR.START = Receive start
RFMR.FSOS = None (Input)
RCMR.START = any on RF (edge/level)
Fix/Workaround
None.
The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:
Clock is CKDIV
The START is selected on either a frame synchro edge or a level,
Frame synchro data is enabled,
Transmit clock is gated on output (through CKO field).
Fix/Workaround
Transmit or receive CLOCK must not be gated (by the mean of CKO field) whenSTART con-
dition is performed on a generated frame synchro.
IN and OUT tokens are sent every 1 ms (Full Speed).
Fix/Workaround
For longer polling time, the software must freeze the pipe for the desired period in order to
prevent any "extra" token.
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.