AT90PWM216-16SE ATMEL [ATMEL Corporation], AT90PWM216-16SE Datasheet - Page 255

• Manufacturer Part Number: AT90PWM216-16SE
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable flash
• Manufacturer: ATMEL [ATMEL Corporation]

AT90PWM216/316
chronization is done automatically by the ADC interface in such a way that the sample-and-hold
occurs at a specific phase of CK
. A conversion initiated by the user (i.e., all single conver-
ADC2
sions, and the first free running conversion) when CK
is low will take the same amount of
ADC2
time as a single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A
conversion initiated by the user when CK
is high will take 14 ADC clock cycles due to the
ADC2
synchronization mechanism.
The normal way to use the amplifier is to select a synchronization clock via the AMPxTS1:0 bits
in the AMPxCSR register. Then the amplifier can be switched on, and the amplification is done
on each synchronization event. The amplification is done independently of the ADC.
In order to start an amplified Analog to Digital Conversion on the amplified channel, the ADMUX
must be configured as specified on
Table 21-4 on page
250.
The ADC starting is done by setting the ADSC (ADC Start conversion) bit in the ADCSRB
register.
Until the conversion is not achieved, it is not possible to start a conversion on another channel.
The conversion takes advantage of the amplifier characteristics to ensure minimum conversion
time.
As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion
is started. In order to have a better understanding of the functioning of the amplifier synchroniza-
tion, a timing diagram example is shown
Figure
21-15.
In case the amplifier output is modified during the sample phase of the ADC, the on-going con-
version is aborted and restarted as soon as the output of the amplifier is stable as shown
Figure
21-16.
The only precaution to take is to be sure that the trig signal (PSC) frequency is lower than
ADCclk/4.
t is also possible to auto trigger conversion on the amplified channel. In this case, the conversion
is started at the next amplifier clock event following the last auto trigger event selected thanks to
the ADTS bits in the ADCSRB register. In auto trigger conversion, the free running mode is not
possible unless the ADSC bit in ADCSRA is set by soft after each conversion.
Only PSC sources can auto trigger amplified conversion. In this case, the core must have a
clock synchronous with the PSC; if the PSC uses the PLL clock, the core must use PLL/4
clock source.
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