AT90PWM216-16SE ATMEL [ATMEL Corporation], AT90PWM216-16SE Datasheet - Page 205

• Manufacturer Part Number: AT90PWM216-16SE
• Description: 8-bit Microcontroller with 16K Bytes In-System Programmable flash
• Manufacturer: ATMEL [ATMEL Corporation]

18.10.3
7710D–AVR–08/09
USART Control and Status Register B – UCSRB
• Bit 2 – UPE: USART Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received and the
Parity Checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer
(UDR) is read. Always set this bit to zero when writing to UCSRA.
This bit is also valid in EUSART mode only when data bits are level encoded (there is no parity
in Manchester mode).
• Bit 1 – U2X: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-
chronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-
bling the transfer rate for asynchronous communication.
This bit is available in both USART and EUSART modes.
• Bit 0 – MPCM: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCM bit is written to
one, all the incoming frames received by the USART Receiver that do not contain address infor-
mation will be ignored. The Transmitter is unaffected by the MPCM setting. For more detailed
information see
This mode is unavailable when the EUSART mode is set.
• Bit 7 – RXCIE: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt
will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is writ-
ten to one and the RXC bit in UCSRA is set.
This bit is available for both USART and EUSART modes.
• Bit 6 – TXCIE: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt
will be generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG is writ-
ten to one and the TXC bit in UCSRA is set.
This bit is available for both USART and EUSART mode.
• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE flag. A Data Register Empty interrupt will
be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDRE bit in UCSRA is set.
This bit is available for both USART and EUSART mode.
Bit
Read/Write
Initial Value
RXCIE
“Multi-processor Communication Mode” on page
R/W
7
0
TXCIE
R/W
6
0
UDRIE
R/W
5
0
RXEN
R/W
4
0
TXEN
R/W
3
0
UCSZ2
AT90PWM216/316
R/W
2
0
202.
RXB8
R
1
0
TXB8
R/W
0
0
UCSRB
205