PIC24FJ16GA MICROCHIP [Microchip Technology], PIC24FJ16GA Datasheet - Page 145

• Manufacturer Part Number: PIC24FJ16GA
• Description: 28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

15.0
The Inter-Integrated Circuit™ (I
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, display drivers, A/D
Converters, etc.
The I
• Independent master and slave logic
• 7-bit and 10-bit device addresses
• General call address, as defined in the I
• Clock stretching to provide delays for the
• Both 100 kHz and 400 kHz bus specifications.
• Configurable address masking
• Multi-Master modes to prevent loss of messages
• Bus Repeater mode, allowing the acceptance of
• Automatic SCL
A block diagram of the module is shown in Figure 15-1.
15.1
The I
cannot be reassigned to alternate pins using peripheral
pin select. To allow some flexibility with peripheral
multiplexing, the I2C1 module in all devices, can be
reassigned to the alternate pins, designated as ASCL1
and ASDA1 during device configuration.
Pin assignment is controlled by the I2C1SEL Configu-
ration bit; programming this bit (= 0) multiplexes the
module to the ASCL1 and ASDA1 pins.
© 2008 Microchip Technology Inc.
Note:
processor to respond to a slave data request
in arbitration
all messages as a slave regardless of the address
2
2
C modules are tied to fixed pin assignments, and
C module supports these features:
INTER-INTEGRATED CIRCUIT
(I
Peripheral Remapping Options
2
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
”Section 24. Inter-Integrated Circuit
(I
C™)
2
C™)” (DS39702).
Family
2
Reference
C™) module is a serial
2
C protocol
Manual”,
PIC24FJ64GA004 FAMILY
Preliminary
15.2
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Wait for and verify an Acknowledge from the
11. Enable master reception to receive serial
12. Generate an ACK or NACK condition at the end
13. Generate a Stop condition on SDAx and SCLx.
Assert a Start condition on SDAx and SCLx.
Send the I
with a write indication.
Wait for and verify an Acknowledge from the
slave.
Send the first data byte (sometimes known as
the command) to the slave.
Wait for and verify an Acknowledge from the
slave.
Send the serial memory address low byte to the
slave.
Repeat steps 4 and 5 until all data bytes are
sent.
Assert a Repeated Start condition on SDAx and
SCLx.
Send the device address byte to the slave with
a read indication.
slave.
memory data.
of a received byte of data.
Communicating as a Master in a
Single Master Environment
2
C device address byte to the slave
DS39881C-page 143