PIC24FJ16GA MICROCHIP [Microchip Technology], PIC24FJ16GA Datasheet - Page 128

• Manufacturer Part Number: PIC24FJ16GA
• Description: 28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

PIC24FJ64GA004 FAMILY
12.1
REGISTER 12-1:
DS39881C-page 126
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-8
bit 7
bit 6-5
bit 4
bit 3
bit 2-0
Note 1:
ICTMR
R/W-0
U-0
—
Input Capture Registers
RPINRx (ICxRx) must be configured to an available RPn pin. For more information, see Section 9.4
“Peripheral Pin Select”.
Unimplemented: Read as ‘0’
ICSIDL: Input Capture x Module Stop in Idle Control bit
1 = Input capture module will halt in CPU Idle mode
0 = Input capture module will continue to operate in CPU Idle mode
Unimplemented: Read as ‘0’
ICTMR: Input Capture x Timer Select bit
1 = TMR2 contents are captured on capture event
0 = TMR3 contents are captured on capture event
ICI1:ICI0: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
ICOV: Input Capture x Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
ICBNE: Input Capture x Buffer Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
ICM2:ICM0: Input Capture x Mode Select bits
111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edge
110 = Unused (module disabled)
101 = Capture mode, every 16th rising edge
100 = Capture mode, every 4th rising edge
011 = Capture mode, every rising edge
010 = Capture mode, every falling edge
001 = Capture mode, every edge (rising and falling) – ICI<1:0> bits do not control interrupt generation
000 = Input capture module turned off
R/W-0
ICI1
U-0
—
ICxCON: INPUT CAPTURE x CONTROL REGISTER
detect only, all other control bits are not applicable)
for this mode
HC = Hardware Clearable bit
W = Writable bit
‘1’ = Bit is set
ICSIDL
R/W-0
R/W-0
ICI0
R-0, HC
ICOV
U-0
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
R-0, HC
ICBNE
U-0
—
ICM2
R/W-0
U-0
—
(1)
© 2008 Microchip Technology Inc.
x = Bit is unknown
ICM1
R/W-0
U-0
—
(1)
ICM0
R/W-0
U-0
—
(1)
bit 8
bit 0