PIC24FJ16GA MICROCHIP [Microchip Technology], PIC24FJ16GA Datasheet - Page 137

• Manufacturer Part Number: PIC24FJ16GA
• Description: 28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

To set up the SPI module for the Enhanced Buffer
Master mode of operation:
1.
2.
3.
4.
5.
6.
FIGURE 14-2:
© 2008 Microchip Technology Inc.
SSx/FSYNCx
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1 and
SPIxCON2
(SPIxCON1<5>) = 1.
Clear the SPIROV bit (SPIxSTAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
SDOx
SCKx
SDIx
Clear the SPIxIF bit in the respective IFSx
register.
Set the SPIxIE bit in the respective IECx
register.
Write the SPIxIP bits in the respective IPCx
register.
Read SPIxBUF
Control
registers
Transfer
Sync
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
Receive Buffer
8-Level FIFO
bit0
with
SPIxSR
Control
SPIxBUF
Clock
Shift Control
Transmit Buffer
8-Level FIFO
MSTEN
PIC24FJ64GA004 FAMILY
Preliminary
Transfer
Write SPIxBUF
Select
Edge
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
8.
16
Clear the SPIxBUF register.
If using interrupts:
• Clear the SPIxIF bit in the respective IFSx
• Set the SPIxIE bit in the respective IECx
• Write the SPIxIP bits in the respective IPCx
Write the desired settings to the SPIxCON1 and
SPIxCON2
(SPIxCON1<5>) = 0.
Clear the SMP bit.
If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.
Clear the SPIROV bit (SPIxSTAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
register.
register.
register to set the interrupt priority.
Secondary
Prescaler
1:1 to 1:8
Internal Data Bus
registers
1:1/4/16/64
Prescaler
Primary
with
DS39881C-page 135
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
F
CY
MSTEN