KS8893ML MICREL [Micrel Semiconductor], KS8893ML Datasheet - Page 103
![no-image](/images/no-image-200.jpg)
KS8893ML
Manufacturer Part Number
KS8893ML
Description
Integrated 3-Port 10/100 Managed Switch with PHYs Preliminary Data Sheet Rev. 1.0
Manufacturer
MICREL [Micrel Semiconductor]
Datasheet
1.KS8893ML.pdf
(106 pages)
- Current page: 103 of 106
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Reset Timing
The KS8893M should be powered up with the VDD core voltages (VDDC, VDDA, VDDAP) applied before the
VDDIO and transceiver voltages (VDDIO, VDDATX, VDDARX). In the worst case, VDD core, VDDIO and
transceiver voltages can be applied simultaneously. For the KS8893ML, there is no power sequence requirement.
Additional, reset timing requirements are summarized in the following figure and table.
After the de-assertion of reset, it is recommended to wait a minimum of 100 us before starting programming on
the managed interface (I2C slave, SPI slave, SMI, MIIM).
June 2005
Parameter
t
t
t
t
cs
ch
sr
rc
Output Pin
Strap-In
Voltage
Strap-In/
RST_N
Supply
Stable supply voltages to reset high
Configuration setup time
Configuration hold time
Reset to strap-in pin output
Value
Description
Table 31. Reset Timing Parameters
Figure 27. Reset Timing
tsr
103
tcs
tch
trc
Min
10
50
50
50
Max
Units
ms
ns
ns
us
M9999-063005
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