IR3895MPBF IRF [International Rectifier], IR3895MPBF Datasheet - Page 38
IR3895MPBF
Manufacturer Part Number
IR3895MPBF
Description
16A HIGHLY INTERGRATED SUPLRBUCK
Manufacturer
IRF [International Rectifier]
Datasheet
1.IR3895MPBF.pdf
(43 pages)
LAYOUT RECOMMENDATIONS
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to perform
with less than expected results.
Make the connections for the power components in
the top layer with wide, copper filled areas or
polygons. In general, it is desirable to make proper use
of power planes and polygons for power distribution
and heat dissipation.
The inductor, output capacitors and the IR3899 should
be as close to each other as possible. This helps to
reduce the EMI radiated by the power traces due to
the high switching currents through them. Place the
input capacitor directly at the PVin pin of IR3899.
The feedback part of the system should be kept away
from the inductor and other noise sources.
Compensation parts
should be placed
as close as possible
to the Comp pin
Resistor Rt and Vref
decoupling cap should
be placed as close as
possible to their pins
38
AUGUST 08, 2012 | DATA SHEET| Rev 3.1
Figure 47a: IRDC3895 Demo board Layout Considerations – Top layer
Single‐Input Voltage, Synchronous Buck Regulator
- 38 -P
16A Highly Integrated SupIRBuck
The critical bypass components such as capacitors for
Vin, Vcc and Vref should be close to their respective pins.
It is important to place the feedback components
including feedback resistors and compensation
components close to Fb and Comp pins.
In a multilayer PCB use one layer as a power ground
plane and have a control circuit ground (analog ground),
to which all signals are referenced. The goal is to localize
the high current path to a separate loop that does not
interfere with the more sensitive analog control function.
These two grounds must be connected together on the
PC board layout at a single point. It is recommended to
place all the compensation parts over the analog ground
plane in top layer.
The Power QFN is a thermally enhanced package. Based
on thermal performance it is recommended to use at
least a 4‐layers PCB. To effectively remove heat from the
device the exposed pad should be connected to the
ground plane using vias. Figures 46a‐d illustrates the
implementation of the layout guidelines outlined above,
on the IRDC3899 4‐layer demo board.
Enough copper & minimum
ground length path between
Input and Output
All bypass caps should be
placed as close as possible
to their connecting pins
Switch Node
IR3895
PD‐97746