IR3895MPBF IRF [International Rectifier], IR3895MPBF Datasheet - Page 24

• Manufacturer Part Number: IR3895MPBF
• Description: 16A HIGHLY INTERGRATED SUPLRBUCK
• Manufacturer: IRF [International Rectifier]

OVER‐VOLTAGE PROTECTION (OVP)
Over‐voltage protection in IR3895 is achieved by
comparing sense pin voltage Vsns to a pre‐set threshold.
In non‐tracking mode, OVP threshold can be set at
1.2*Vref; in tracking mode, it can be at 1.2*Vp. When Vsns
exceeds the over voltage threshold, an over voltage trip
signal asserts after 2us (typical.) delay. Then the high side
drive signal HDrv is turned off immediately, PGood flags
low. The low side drive signal is kept on until the Vsns
voltage drops below the threshold. After that, HDrv is
latched off until a reset performed by cycling either Vcc or
Enable.
Vsns voltage is set by the voltage divider connected to the
output and it can be programmed externally. Figure 18
shows the timing diagram for OVP in non‐tracking mode.
Figure 18: Timing Diagram for OVP in non‐tracking mode
Figure 17: Vp Sequence and Vref Margin
24
AUGUST 08, 2012 | DATA SHEET| Rev 3.1
Single‐Input Voltage, Synchronous Buck Regulator
- 24 -P
16A Highly Integrated SupIRBuck
SOFT‐STOP (S_CTRL)
Soft‐stop function can make output voltage discharge
gradually. To enable this function, S_Ctrl is kept low first
when EN goes high. Then S_Ctrl is pulled high to cross the
logic level threshold (typical 2V), the internal soft‐start
ramp is initiated. So Vo follows Intl_SS to ramp up until it
reaches its steady state. In soft‐stop process, S_Ctrl needs
to be pulled low before EN goes low. After S_Ctrl goes
below its threshold, a decreasing ramp is generated at
Intl_SS with the same slope as in soft‐start ramp. Vo
follows this ramp to discharge softly until shutdown
completely. Figure 19 shows the timing diagram of S_Ctrl
controlled soft‐start and soft‐stop.
If the falling edge of Enable signal asserts before S_Ctrl
falling edge, the converter is still turned off by Enable.
Both gate drivers are turned off immediately and Vo
discharges to zero. Figure 20 shows the timing diagram
of Enable controlled soft‐start and soft‐stop. Soft stop
feature ensures that Vout discharges and also regulates
the current precisely to zero with no undershoot.
Enable
S_Ctrl
Vout
_SS
Enable
S_Ctrl
Intl
Vout
_SS
Intl
0
0
0
Figure 20: Timing Diagram for Enable controlled
0
0
0
Figure 19: Timing Diagram for S_Ctrl controlled
0
0
0.65V
0.15V
0.15V
0.65V
1.2V
Soft Start/Shutdown
Soft Start/Soft Stop
IR3895
PD‐97746
1.0V
0.65V
0.15V