IR3895MPBF IRF [International Rectifier], IR3895MPBF Datasheet - Page 20

• Manufacturer Part Number: IR3895MPBF
• Description: 16A HIGHLY INTERGRATED SUPLRBUCK
• Manufacturer: IRF [International Rectifier]

I
I
ΔI=Inductor ripple current
THERMAL SHUTDOWN
Temperature sensing is provided inside IR3895. The trip
threshold is typically set to 145
exceeded, thermal shutdown turns off both MOSFETs and
resets the internal soft start.
Automatic restart is initiated when the sensed
temperature drops within the operating range. There is
a 20
EXTERNAL SYNCHRONIZATION
IR3895 incorporates an internal phase lock loop (PLL)
circuit which enables synchronization of the internal
oscillator to an external clock. This function is important to
avoid sub‐harmonic oscillations due to beat frequency for
embedded systems when multiple point‐of‐load (POL)
regulators are used. A multi‐function pin, Rt/Sync, is used
to connect the external clock. If the external clock is
present before the converter turns on, Rt/Sync pin can be
connected to the external clock signal solely and no other
resistor is needed. If the external clock is applied after the
converter turns on, or the converter switching frequency
needs to toggle between the external clock frequency and
the internal free‐running frequency, an external resistor
from Rt/Sync pin to Gnd is required to set the free‐running
frequency.
When an external clock is applied to Rt/Sync pin after the
converter runs in steady state with its free‐running
I
OCP
LIMIT
OCP
= DC current limit hiccup point
= Current limit Valley Point
o
C hysteresis in the thermal shutdown threshold.

I
LIMIT
20


2
Figure 8: Timing Diagram for
I
AUGUST 08, 2012 | DATA SHEET| Rev 3.1
Current Limit Hiccup
(2)
o
C. When trip threshold is
Single‐Input Voltage, Synchronous Buck Regulator
- 20 -P
16A Highly Integrated SupIRBuck
frequency, a transition from the free‐running frequency to
the external clock frequency will happen. This transition is
to gradually make the actual switching frequency equal to
the external clock frequency, no matter which one is
higher. On the contrary, when the external clock signal is
removed from Rt/Sync pin, the switching frequency is also
changed to free‐running gradually. In order to minimize
the impact from these transitions to output voltage, a
diode is recommended to add between the external clock
and Rt/Sync pin, as shown in Fig9a. Figure 9b shows the
timing diagram of these transitions.
An internal circuit is used to change the PWM ramp slope
according to the clock frequency applied on Rt/Sync pin.
Even though the frequency of the external synchronization
clock can vary in a wide range, the PLL circuit will make
sure that the ramp amplitude is kept constant, requiring no
adjustment of the loop compensation. Vin variation also
affects the ramp amplitude, which will be discussed
separately in Feed‐Forward section.
Figure 9a: Configuration of External Synchronization
Figure 9: Timing Diagram for Synchronization
to the external clock (Fs1>Fs2 or Fs1<Fs2)
Rt/Sync
IR3895
Gnd
IR3895
PD‐97746