EMC12 ETC2 [List of Unclassifed Manufacturers], EMC12 Datasheet - Page 21

• Manufacturer Part Number: EMC12
• Description: Audio Interface for the EmPack System
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

DSP has no valid data to send on one or more time slots such as when a frame slip is detected on an
incoming E1 or T1 stream.
The EMC12 hardware provides a mechanism for the DSP to control the TDM valid signal that
accompanies each TDM data bus. This is accomplished by using pairs of consecutive TDM time slots.
For each pair of time slots to be connected in this way, the first time slot is given a Source control value
of 0xC (DSP Sends TDM Valid Control) and the second time slot is given a Source control value if 0xD
(DSP Sends TDM Data). These control word pairs must be encoded for the same TDM bus on
consecutive time slots.
When pairs of time slot control words are encoded this way, they behave as though the second time slot
was a continuation slot. The DSP receives one OLD signal for the pair, at the beginning of the first time
slot. The DSP is then expected to transmit 16 bits of serial data. The first 8 bits contain the TDM valid
information and the second 8 bits is the byte of data to be driven as TDM data on the selected TDM bus.
The 2nd bit of the valid information is sampled by the hardware and used to control the TDM valid signal
for the second time slot of the pair.
The examples below show how to build a 16-bit serial data word in the DSP program for a data byte that
is valid and one that is invalid. The bit ordering assumes that the DSP’s IOC register is set to transmit
the most significant bit of the serial output buffer first and that it will be transmitting serial data from the
memory referenced by serial_out_buffer using serial DMA output.
1.3.5 TDM FIFO
The TDM control words for an entire TDM frame are stored in one of two FIFOs on the board. The
FIFO being used for the current TDM frame is the active FIFO, the other is called the inactive FIFO.
The inactive FIFO can be read/written by the base board through the TCDR using PIO read/write
operations. Writing a ‘1’ to the FIFO_RT (FIFO Retransmit) bit in BCR1 resets the FIFO read pointer.
The word read from the TCDR after a FIFO Retransmit is the first word in the FIFO.
To load a new TDM control map, write a ‘1’ to the FIFO_RESET bit in BCR1. This resets the
read/write pointers of the FIFO. Then write each word (9-bit) of the map to the TCDR. A maximum of
1024 words can be written. The 1024th word is written to the LTCW register instead of the FIFO.
When the entire map is loaded, write a ‘1’ to the SWITCH_FIFO bit in BCR1. The inactive FIFO will
become active at the next frame boundary. The deactivated FIFO can be read and written by the base
board after the switch.
09 Jan 2006
unsigned short serial_out_buffer[64];
char out_data[64]
int data_valid[64];
for (i = 0; i < 64; ++i)
{
}
serial_out_buffer[i] = out_data[i];
if (data_valid[i])
serial_out_buffer[i] |= 0x4000;
Communication Automation Corporation
EMC12 Hardware Reference Manual
1-17