EMC12 ETC2 [List of Unclassifed Manufacturers], EMC12 Datasheet - Page 20

• Manufacturer Part Number: EMC12
• Description: Audio Interface for the EmPack System
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

1.3.3 TDM Validity and Conditional Transfers
Each TDM bus has a data signal and a valid signal. The valid signal is used to indicate whether a given
time-slot contains valid data. When a DSP is selected as the source of a TDM bus for a time-slot, the
OBE signal from the DSP is sampled before OLD pulse is generated. If OBE is low, indicating that the
DSP’s serial buffer has data to send, the OLD pulse is generated and the valid signal is driven high for
one bit clock. The valid signal is also driven high for one bit clock when a Codec is selected as the
source of a TDM bus. If OBE is high, indicating that the DSP’s serial output buffer is empty, the OLD
pulse is suppressed, and the valid signal is driven low for 1 bit clock.
When a DSP is selected to conditionally receive from a TDM bus, the valid line of the that bus is sampled
before the ILD pulse is generated. If the valid signal is low, the ILD pulse is suppressed and the data on
the bus is ignored.
1.3.4 Programmable TDM Validity
For the conditional TDM transfers described above, the hardware between the DSP and the TDM
subsystem determines whether a time slot’s data is valid based on the state of the DSP’s OBE signal.
Some applications may require the DSP to determine when the data it has to send is valid or not. For
example when dealing with isochronously generated data (such as E1 or T1 framers) the DSP will be
sending data at a constant rate and on a fixed and multiple number of time slots per TDM frame. In
order to maintain synchronization with the TDM frame, the DSP must be allowed to transmit serial data
for every time slot on which it is connected to the TDM bus. However there may be times when the
09 Jan 2006
T D M V A L I D
T D M D A T A
I N T R E Q 1
L M S Y N C
S L C K
O B E
OLD
ILD
IBF
D O
DI
Communication Automation Corporation
EMC12 Hardware Reference Manual
Figure 1-3: TDM Timing
D 0
D 1
D 0
D 2
D 1
D 3
D 2
D 0
D 4
D 3
D 1
D 5
D 4
D 2
D 6
D 5
D 3
D 7
D 6
D 4
OLD suppressed
D 7
D 5
D 6
D 7
ILD suppressed
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