MC35XS3400CHFK FREESCALE [Freescale Semiconductor, Inc], MC35XS3400CHFK Datasheet - Page 31

• Manufacturer Part Number: MC35XS3400CHFK
• Description: Quad High Side Switch (Quad 35 mOhm)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Table 15. Current Sense Ratio Selection
ADDRESS A
REGISTER (OCR)
corresponding output over-current protection through the
SPI. Each output “s” is independently selected for
configuration based on the state of the D14 : D13 bits
(Table
curve and D[5:4] bits inrush curve for selected output, as
shown
Table 16. Cooling and Inrush Curve Selection
Table 17. Inrush Curve Selection
replaced by OCHI2 during t
current levels in steady state, as defined in
Analog Integrated Circuit Device Data
Freescale Semiconductor
I
I
I
I
I
I
I
I
I
I
Figure 13. Over-current profile with OCHI bit set to ‘1’
OCH
OCH2
OC1
OC2
OC3
OC4
OCLO4
OCLO3
OCLO2
OCLO1
The OCR_s register allows the MCU to configure
D[7:6] bits allow to MCU to programmable bulb cooling
A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is
The wire harness is protected by one of four possible
BC1_s (D7)
OC1_s (D5)
1
CSNS_high_s (D0)
t
12).
Table 16
OC1
0
0
1
1
0
0
1
1
t
OC2
t
OC3
0
1
1
A
and
t
0
OC4
100 — OUTPUT OVER-CURRENT
Table
BC0_s (D6)
OC0_s (D4)
t
OC5
0
1
0
1
17.
0
1
0
1
OC1
, as shown
t
OC6
Current Sense Ratio
Profile Curves Speed
Profile Curves Speed
CRS0 (default)
t
medium (default)
OC7
slow (default)
CRS1
Figure
Table
very slow
medium
medium
slow
fast
fast
13.
18.
Time
Table 18. Output Steady State Selection
mode, as described
Table 19. Over-current Mode Selection
ADDRESS 00101 — GLOBAL CONFIGURATION
REGISTER (GCR)
through the SPI.
detector. A logic [1] on VDD_FAIL_en bit allows transitioning
to Fail-safe mode for V
module. A logic [1] on PWM_en bit allows control of the
outputs HS[0:3] with PWMR register (the direct input states
are ignored).
reference by PWM module, as described in the following
Table
Table 20. PWM Module Selection
feedback on CSNS output pin, as shown in
Table 21. CSNS Reporting Selection
TEMP_en
OCLO1 (D2) OCLO0 (D1)
OC_mode_s (D0)
PWM_en (D7) CLOCK_sel (D6)
Bit D0 (OC_mode_sel) allows to select the over-current
The GCR register allows the MCU to configure the device
Bit D8 allows the MCU to enable or disable the V
Bit D7 allows the MCU to enable or disable the PWM
Bit D6 (CLOCK_sel) allows to select the clock used as
Bits D5:D4 allow the MCU to select one of two analog
(D5)
X
0
1
0
0
1
1
20.
0
1
1
0
1
CSNS_en
(D4)
0
1
0
inrush current and bulb cooling management
0
1
0
1
Table
only inrush current management (default)
DD
X
0
1
current recopy of selected output (D3:2]
LOGIC COMMANDS AND REGISTERS
< V
FUNCTIONAL DEVICE OPERATION
19.
temperature on GND flag
DD(FAIL).
CSNS tri-stated (default)
Over-current Mode
CSNS reporting
Steady State Current
PWM module enabled with
PWM module enabled with
internal calibrated clock
OCLO2 (default)
external clock from IN0
PWM module disabled
bits)
OCLO3
OCLO4
OCLO1
PWM module
(default)
Table
21.
DD
35XS3400
failure
31