MC35XS3400CHFK FREESCALE [Freescale Semiconductor, Inc], MC35XS3400CHFK Datasheet - Page 23

• Manufacturer Part Number: MC35XS3400CHFK
• Description: Quad High Side Switch (Quad 35 mOhm)
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

SLEEP MODE
battery voltage (VPWR) prior to any I/O transitions. This is
also the state of the device when the WAKE and
IN_ON[0:3] are logic [0]. In the Sleep mode, the output and
all unused internal circuitry, such as the internal regulator, are
off to minimize draw current. In addition, all SPI-configurable
features of the device are as if set to logic [0].
NORMAL MODE
the outputs HS[0:3] are under control, as defined by hson
signal:
PWM_en ) or (On bit [x] and Duty_cycle[x] and PWM_en).
Analog Integrated Circuit Device Data
Freescale Semiconductor
The 35XS3400 is in Sleep mode when:
• V
• wake-up = 0,
• fail = X,
• fault = X.
This is the Default mode of the device after first applying
The 35XS3400 is in Normal mode when:
• V
• wake-up = 1,
• fail = 0,
• fault = 0.
In this mode, the NM bit is set to lfault_contrologic [1] and
hson[x] = ( ( (IN[x] and DIR_dis[x]) or On bit[x] ) and
PWR
PWR
Fail Safe
and V
and V
(wake-up=0)
DD
DD
are within the normal voltage range,
are within the normal voltage range,
(wake-up=1) and
(fail=1)
and (fault=0)
(fail=1) and
(wake-up=1)
and (fault=1)
(fail=0) and (wake-up=1) and (fault=0)
(fail=1) and (wake-up=1) and (fault=0)
(fail=1)
(wake-up=1)
and (fault=0)
(wake-up=0)
Figure 11. Operating Modes
RST
and
and
Fault
Sleep
(wake-up=1)
and (fault=1)
depends on fault_control signal, as defined below:
PWM_en ) or (On bit [x]).
Programmable PWM module
PWM module if PWM_en and On bits are set to logic [1].
clock is the factor 2
(CLOCK_sel bit). The outputs HS[0:3] can be controlled in
the range of 5% to 98% with a resolution of 7 bits of duty-
cycle
Table 7. Output PWM Resolution
delay (number of PWM clock rising edges) to improve overall
EMC behavior of the light module
In this mode and also in Fail-safe, the fault condition reset
fault_control[x] = ( (IN_ON[x] and DIR_dis[x]) and
The outputs HS[0:3] are controlled by the programmable
The clock frequency from IN0 input pin or from internal
The timing includes seven programmable PWM switching
On bit
(Table
0
1
1
1
1
1
(fail=0)
(wake-up=1)
and (fault=1)
(fail=0)
(wake-up=1)
and (fault=0)
7). The state of other IN pin is ignored.
(fail=0) and (wake-up=1) and (fault=0)
(wake-up=0)
Duty-cycle
0000000
0000001
0000010
1111111
and
and
7
X
n
(128) of the output PWM frequency
FUNCTIONAL DEVICE OPERATION
Normal
PWM ((n+1)/128 duty-cycle)
PWM (1/128 duty-cycle)
PWM (2/128 duty-cycle)
PWM (3/128 duty-cycle)
(Table
OPERATIONAL MODES
Output state
fully ON
8).
OFF
35XS3400
23