ADP5061 AD [Analog Devices], ADP5061 Datasheet - Page 6

• Manufacturer Part Number: ADP5061
• Description: Tiny I2C Programmable Linear Battery Charger
• Manufacturer: AD [Analog Devices]

Bus Free Time Between a Stop and a Start Condition
ADP5061
RECOMMENDED INPUT AND OUTPUT CAPACITANCES
Table 2.
Parameter
CAPACITANCES
I
Table 3.
Parameter
I
1
2
Timing Diagram
2
2
Guaranteed by design.
A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL (see Figure 2).
C-COMPATIBLE INTERFACE
C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
VINx
CBP
ISO_Sx
ISO_Bx
Capacitive Load for Each Bus Line
SCL Clock Frequency
SCL High Time
SCL Low Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Hold Time for Start/Repeated Start
Setup Time for Stop Condition
Rise Time of SCL/SDA
Fall Time of SCL/SDA
Pulse Width of Suppressed Spike
SDA
SCL
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
1
S
t
LOW
2
Symbol
C
C
C
C
VIN
BP
ISO_S
ISO_B
t
R
t
HD, DAT
Min
4
6
20
10
t
SU, DAT
t
HIGH
Typ
10
47
22
Figure 2. I
Rev. 0 | Page 6 of 44
Symbol
f
t
C
t
t
t
t
t
t
t
t
t
t
SCL
HIGH
LOW
SU, DAT
HD, DAT
SU, STA
HD, STA
BUF
SU, STO
R
F
SP
t
S
F
2
t
C Timing Diagram
BU, STA
Max
10
14
100
t
F
Min
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20
20
0
Sr
Unit
μF
nF
μF
μF
Typ
t
HD, STA
Max
400
400
0.9
300
300
50
Test Conditions/Comments
Effective capacitance
Effective capacitance
Effective capacitance
Effective capacitance
Unit
pF
kHz
µs
µs
ns
µs
µs
µs
µs
µs
ns
ns
ns
t
SP
t
BU, STO
Test Conditions/Comments
t
R
P
Data Sheet
S
t
BUF