NCP5331_05 ONSEMI [ON Semiconductor], NCP5331_05 Datasheet - Page 26

• Manufacturer Part Number: NCP5331_05
• Description: Two-Phase PWM Controller with Integrated Gate Drivers
• Manufacturer: ONSEMI [ON Semiconductor]

4. Input Inductor Selection
the power source will accomplish two objectives. First, it
will isolate the voltage source and the system from the noise
generated in the switching supply. Second, it will limit the
inrush current into the input capacitors at power up. Large
inrush currents will reduce the expected life of the input
capacitors. The inductor’s limiting effect on the input
current slew rate becomes increasingly beneficial during
load transients.
the first few PWM cycles immediately after a step−load
change is applied as shown in Figure 31. When the load is
applied, the output voltage is pulled down very quickly.
Current through the output inductors will not change
instantaneously so the initial transient load current must be
conducted by the output capacitors. The output voltage will
step downward depending on the magnitude of the output
current (I
capacitors (ESR
capacitors (N
current is shared equally between the two phases, the output
voltage at full, transient load will be
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
voltage across the output inductor can be calculated as
cause its current to increase linearly with time. The slew rate
of this current can be calculated from
V CORE,FULL−LOAD +
DV Lo + V IN * V CORE,FULL−LOAD
The use of an inductor between the input capacitors and
The worst case input current slew rate will occur during
When the control MOSFET (Q1 in Figure 31) turns ON,
The differential voltage across the output inductor will
V CORE,NO−LOAD * (I O,MAX 2) @ ESR OUT N OUT
+ V IN * V CORE,NO−LOAD
O,MAX
) (I O,MAX 2) @ ESR OUT N OUT
OUT
+
−
), the per capacitor ESR of the output
OUT
) as shown in Figure 31. Assuming the load
dI Lo dt + DV Lo Lo
5
Vi
12 V
I
), and the number of the output
Li
16MBZ1500M10X20
TBD
Li
13 m/5 = 2.6 m
MAX dI/dt occurs in
first few PWM cycles.
Vi(t = 0) = 12 V
ESR
Figure 31. Calculating the Input Inductance
Ci
Ci
+
V
Ci
Q1
http://onsemi.com
(14)
(15)
(16)
NCP5331
SWNODE
26
Q2
capacitors must initially deliver the vast majority of the
input current. The amount of voltage drop across the input
capacitors (DV
capacitors (N
current in the output inductor according to
inductor (V
the input voltage, V
drop across the input capacitors, DV
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from
where dI
slew rate.
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality input voltage
“sag,” lower capacitor ESRs, and stray inductance will help
reduce the slew rate of the input current.
support the maximum current without saturating the
magnetic. Also, for an inexpensive iron powder core, such
as the −26 or −52 from Micrometals, the inductance “swing”
with dc bias must be taken into account − inductance will
decrease as the dc input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
Current changes slowly in the input inductor so the input
Before the load is applied, the voltage across the input
The input inductance value calculated from Equation 18
As with the output inductor, the input inductor must
729 nH
I
Lo
Lo
IN
DV Ci + ESR IN N IN @ dI Lo dt @ t ON
/dt
Li
IN
) is very small − the input capacitors charge to
MAX
+ ESR IN N IN @ dI Lo dt @ D f SW
+
Ci
), their per capacitor ESR (ESR
Li MIN + V Li
ESR
19 m/6 = 3.2 m
Co
6
) is determined by the number of input
Vo(t = 0) = 1.225 V
is the maximum allowable input current
IN
16MBZ1000M10X16
Co
+ DV Ci
. After the load is applied the voltage
V
OUT
dI IN dt MAX
26 u(t)
dI IN dt MAX
Ci
, appears across the
IN
), and the
(17)
(18)