NCP5331_05 ONSEMI [ON Semiconductor], NCP5331_05 Datasheet - Page 20

• Manufacturer Part Number: NCP5331_05
• Description: Two-Phase PWM Controller with Integrated Gate Drivers
• Manufacturer: ONSEMI [ON Semiconductor]

voltage as the V
through the V
the V
current offsets the V
voltage to decrease.
transient are controlled primarily by power stage output
impedance and the ESR and ESL of the output filter. The
transition between fast and slow positioning is controlled by
the total ramp size and the error amp compensation. If the
current signal (external ramp) size is too large or the error
amp too slow there will be a long transition to the final
voltage after a transient. This will be most apparent with
lower capacitance output filters.
Error Amp Compensation, Tuning, and Soft Start
capacitance (C
between the COMP pin and GND for two reasons. First, this
capacitance stabilizes the transconductance error amplifier.
Values less than a few nF may cause oscillations of the
COMP voltage and increase the output voltage jitter.
Second, this capacitance sets the soft start and hiccup mode
slopes. The
approximately 30 mA during soft start and hiccup mode. No
switching will occur until the COMP voltage exceeds the
Channel Startup Offset (nominally 0.6 V). If C
0.1 mF the 30 mA from the error amplifier will allow the
output to ramp up or down at approximately 30m A/0.1 mF
or 0.3 V/ms or 1.2 V in 4 ms.
below the COMP Discharge Threshold (nominally 0.27 V).
capacitor (R
quickly during transient loading of the converter. Without
this network the error amplifier would have to drive the large
soft start capacitor (C
limit the slew rate of the COMP voltage. The R
network allows the COMP voltage to undergo a step change
of approximately R
amplifier’s inverting input (the V
combination of the resistors R
bandwidth of the error amplifier. The gain of the error
amplifier crosses 0 dB at a high enough frequency to give a
quick transient response, but well below the switching
frequency to minimize ripple and noise on the COMP pin.
A capacitor in parallel with the R
to boost phase near the crossover frequency to improve loop
stability.
V COMP + V CORE @ 0 A ) Channel_Startup_Offset
During no load conditions the V
The response during the first few microseconds of a load
The transconductance error amplifier requires a
The COMP voltage will ramp up to the following value.
The COMP pin will disable the converter when pulled
The RC network between the COMP pin and the soft start
The capacitor (C
DRP
pin increases proportionally and the V
C1
) Int_Ramp ) G CSA @ Ext_Ramp 2
DRP
, C
C1
FB
internal
C1
pin, so none of the V
A1
resistor. When output current increases
+ C
C1
FB
) allows the COMP voltage to slew
) between the COMP pin and the error
C2
C2
I
bias current and causes the output
) directly, which would drastically
COMP
error
in the Applications Diagram)
.
F1
F1
amplifier
and R
FB
resistor (C
DRP
pin) and the parallel
FB
DRP
pin is at the same
bias current flows
F1
determine the
will
) adds a zero
C2
DRP
is set to
C1
http://onsemi.com
source
/C
pin
NCP5331
C1
20
process. First, the no−load and full−load adaptive voltage
positioning (AVP) are set using R
Second, the current sense time constant and error amplifier
gain are adjusted with RSx and C
V
voltage ripple on the COMP pin is examined when the
converter is fully loaded to insure low output voltage jitter.
The exact details of this process are covered in the Design
Procedure section.
Undervoltage Lockout (UVLO)
monitoring two pins. One, intended for the logic and
low−side drivers, is connected to the V
turn−on and 6.15 V turn−off threshold. A second, for the
high side drivers, is connected to the V
turn−on and 6.75 V turn−off threshold. A UVLO fault sets
the fault latch which forces switching to stop and the upper
and lower gate drivers produce a logic low (i.e., all the
MOSFETs are turned OFF). Power good (PGD) is pulled
low when UVLO occurs. The overcurrent/overvoltage latch
is reset by the UVLO signal.
Power Good (PGD) Delay Time
87.5%
power good pin (PGD) will be pulled low by the NCP5331.
When V
impedance. An external pull−up resistor is required on PGD.
threshold, 87.5% DAC, then the “longer” of two timers will
dictate when PGD becomes high impedance. One timer is
internally set to 200 ms and can not be changed. Placing a
capacitor from the C
programmable timer. When V
threshold, a current source will charge C
NOTE:
CORE
Setting up and tuning the error amplifier is a three step
The controller has undervoltage lockout comparators
When V
During soft start, when V
Figure 26. Power Good Delay Operation
during transient loading. Lastly, the peak−to−peak
The PGD timer insures that PGD will transition high
when V
CORE
DAC, or greater than 2.0 V the open−collector
CORE
CORE
is in regulation PGD will become high
is less than the power good threshold,
is in regulation.
PGD
pin to GND sets the second
CORE
F1
CORE
reaches the power good
and R
A1
CCH
CCL
crosses the PGD
while monitoring
DRP
pin with an 8.5 V
pin with an 8.5 V
PGD
, respectively.
starting at