XCF16PVO48C XILINX [Xilinx, Inc], XCF16PVO48C Datasheet - Page 22

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XCF16PVO48C

Manufacturer Part Number
XCF16PVO48C
Description
Platform Flash In-System Programmable Configuration PROMs
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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DS123 (v2.11.1) March 30, 2007
Product Specification
TMS
TDO
TCK
TDI
V
CCJ
Revision
Design
Control
Logic
V
CCO
R
V
CCINT
Figure 12: Configuring Multiple Devices with Design Revisioning in Slave Serial Mode
V
V
V
TDI
TMS
TCK
EN_EXT_SEL
REV_SEL[1:0]
GND
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
CCINT
CCO (2)
CCJ (2)
Notes
1. For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet or FPGA family
2. For compatible voltages, refer to the appropriate data sheet.
3. In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or optionally the CLKOUT
4. For the XCFxxP the CF pin is a bidirectional pin.
External
Oscillator
EN_EXT_SEL
REV_SEL[1:0]
DONE
CF / PROG_B
configuration user guide.
signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used,
then CLKOUT must be tied to a 4.7
must be tied to V
(3)
OE/RESET
CLK
CF
CEO
TDO
CE
D0
(3)
(4)
CCO
via a 4.7 kΩ pull-up resistor.
V
CCJ
V
CCO
V
resistor pulled up to V
CCINT
V
V
V
TDI
TMS
TCK
EN_EXT_SEL
REV_SEL[1:0]
GND
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
CCINT
CCO (2)
CCJ (2)
For the XCFxxP, if CF is not connected to PROG_B, then it
OE/RESET
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMs
CCO
CLK
CF
.
CEO
TDO
CE
D0
(3)
(4)
V
CCO (2)
(1)
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
GND
Xilinx FPGA
Slave Serial
MODE PINS
DOUT
(1)
DIN
CCLK
DONE
INIT_B
PROG_B
TDI
TMS
TCK
GND
Xilinx FPGA
Slave Serial
MODE PINS
ds123_17_012907
TDO
(1)
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