HYB18H1G321AF QIMONDA [Qimonda AG], HYB18H1G321AF Datasheet - Page 38

• Manufacturer Part Number: HYB18H1G321AF
• Description: GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM
• Manufacturer: QIMONDA [Qimonda AG]

Notes
1. 0 °C
2. Data Bus consists of DQ, DM, WDQS.
3. Definitions for IDD:
Rev. 0.92, 2007-10
06122007-MW7D-3G3M
Symbol Parameter/Condition
I
I
DD6
DD7
LOW is defined as VIN = 0.4
TABLE is defined as inputs are stable at a HIGH level.
SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and control signals,
and inputs changing 50% of each data transfer for DQ signals.
≤
Tc
Self Refresh Current
CKE ≤ max(
inputs are STABLE (HIGH).
Operating Bank Interleave Read Current
1. 1-CS Mode: All banks interleaving with CL = CL(min);
and control inputs are STABLE (HIGH) during DESELECT; Data bus inputs are SWITCHING.
2: 2-CS: All banks and all ranks interleaving with CL = CL(min);
t
SWITCHING.
RRD_RR
≤
95 °C
(min);
V
I
IL
out
), external clock off, CK and CK LOW; Address and control inputs are STABLE (HIGH); Data Bus
=0 mA; Address and control inputs are STABLE (HIGH) during DESELECT; Data bus inputs are
×
VDDQ; HIGH is defined as
38
V
IN
=
V
t
RCD
DDQ
=
;
t
t
RCDRD
RCD
=
(min);
t
RCDRD
t
RRD
(min);
=
HYB18H1G321AF–10/11/14
t
t
RRD
RRD
(min);
=
t
RRD
Internet Data Sheet
I
out
(min);
=0 mA; Address
1-Gbit GDDR3
t
RRD_RR
=